What if inheritance occurs for a class with an embedded covergroup?

What behavior are you looking for? Almost any is possible and under your control.

Do you "new" both groups when you create an instance of class B? Do you assign each covergroup a unique instance name? Are you looking at the instance-based report or the type-based report?

reg clk=0;
always #5 clk = !clk;

class A;
     int a;
     
     covergroup cg @(clk);
        option.per_instance = 1;
        v_a: coverpoint a
          iff(reset){}
     endgroup // cg

    function new;
      cg = new;
      cg.option.name = "A_group"; // optional
    endfunction
     
  endclass // A

   class B extends A;
     int b;
      
     covergroup cg @(clk);
        option.per_instance = 1;
        v_b: coverpoint b
          iff(reset){}
     endgroup // cg

     function new;
       super.new;  // optional
       cg = new;
       cg.option.name = "B_group"; // optional
      endfunction 
   endclass // B

  B b;
  initial
  begin
    b = new;
    b.a = 1;
    b.b = 2;
    #10 $finish;
  end

Experiment with different combinations of these and see what results you get.

Thanks TAM1 for your kind reply.

What I expect is to have A and B take their own covergroup, i.e. A with covergroup defined in class A while B has covergroup defined in class B. I've "new" both for A and B as below and assign distinct name for each by calling cg.set_inst_name(), which I think will have the same effect as cg.option.name = "".

reg clk=0;
always #5 clk = !clk;

class A;
    bit[1:0] a;

    covergroup cg @(clk);
    option.per_instance = 1;
    v_a: coverpoint a
        iff(reset){}
    endgroup // cg

function new;
    cg = new;
    cg.option.name = "A_group"; // optional
endfunction

endclass // A

class B extends A;
    bit[1:0] b;

    covergroup cg @(clk);
    option.per_instance = 1;
    v_b: coverpoint b
        iff(reset){}
    endgroup // cg

    function new;
    super.new;  // optional
    cg = new;
    cg.option.name = "B_group"; // optional
    endfunction 
endclass // B

A c_a;
B c_b;
initial
begin
    c_a = new;
    c_b = new;
    c_a.a = 1;
    c_b.a = 2;
    c_b.b = 3;
    #10 $finish;
end

As the instance-based report shows, the A's covergroup still exists in B's covergroup (even without calling super.new in B), is there any way to ignore cov_A in cov_B?

Thanks.

Name         Average, Covered Grade Line Source Code
c_a.A_group  25.00%, 25.00% (1/4)   299  covergroup cg (@clk);
|--v_a       25.00% (1/4)           301  coverpoint a
| --auto[0]  0.00% (0/1)            301  coverpoint a
| |--auto[1] 100.00% (39/1)         301  coverpoint a
| |--auto[2] 0.00% (0/1)            301  coverpoint a
| |--auto[3] 0.00% (0/1)            301  coverpoint a
c_b.A_group  25.00%, 25.00% (1/4)   299  covergroup cg (@clk);
| - -v_a     25.00% (1/4)           301  coverpoint a
| |--auto[0] 0.00% (0/1)            301  coverpoint a
| |--auto[1] 0.00% (0/1)            301  coverpoint a
| |--auto[2]  100.00% (39/1)         301  coverpoint a
| |--auto[3] 0.00% (0/1)            301  coverpoint a
c_b.B_group  25.00%, 25.00% (1/4)   315  covergroup cg (@clk);
|--v_b       25.00% (1/4)           317  coverpoint b
| |--auto[0] 0.00% (0/1)            317  coverpoint b
| |--auto[1] 0.00% (0/1)            317  coverpoint b
| |--auto[2] 0.00% (0/1)            317  coverpoint b
| |--auto[3] 100.00% (39/1)         317  coverpoint b

Of course, you are correct. SystemVerilog will call the default constructor for A even if it isn't explicitly invoked in B's new function. So you'll have to add some code to control the new'ing of A's covergroup yourself.

Class A's new function:

function new(bit make_cg=1);
   if ( make_cg )
   begin
    cg = new;
    cg.option.name = "A_group";
   end
end endfunction

Class B's new function:

function new;
   super.new(0);
   cg = new;
   cg.option.name = "B_group";
endfunction



If you forget to call super.new in the B constructor, you'll get an error message like:



class B extends A;
                 |
xmvlog: *E,FAABP1 (testit.sv,27|17): Task/function call, or property/sequence instance does not specify all required formal arguments.
function new(bit makecg);
                      |
xmvlog: *E,FAABP2 (testit.sv,17|22): Formal argument 'makecg' is missing in the task/function call or property/sequence instance identified by the previous error message.