How to accelerate ncelab phase when invoking irun?

Without any knowledge of your design, or the switches that you're passing to the tool, no, there's nothing we can do to help. Please open a support ticket to get one of the hotline team to work with you on this.

Thanks.

What I expect is to do incremental compiler instead of compile the whole ENV (including all *.v and *.sv files).

I've tried to compile all the *.v into a lib, called rtlLib, and put a line such as,

rtlLib   /PATH/TO/RTLLIB

into the cds.lib. 

I can successfully compile the ENV with the rtlLib. However, the time spent on ncelab is almost the same as before. As a result, the total time is still a bit long.

BTW, if I compiled several modules, who would refer to UVM package, into their libs respectively. An error arguing that 'multiple UVM package was found ....' will be issued eventually.

I am wondering if there is a way to separate the building into each module and construct them in an efficient way.

The compilation flow does build in a lot of dependency information into the compiled libraries, and if you try to do your own dependency management on top of that, you will break the flow. The actual parsing of the files should generally be very fast, so although there is some cost to re-parsing everything, it has the advantage that you won't have any problems with broken dependencies or incorrect partial re-compilations if you try to manage it yourself. Things like compilation unit scopes, macros etc are very easy to get wrong if you're not careful!

If you're hoping to improve your elaboration speed, there are a couple of things to try, depending where the CPU time is spent. Elaboration happens in two stages, first the design topology is computed, parameter values derived, etc. This has to happen every time yo change any code, as the tool cannot predict the impact and dependencies caused by code changes, e.g. if you happen to have hierarchical references into or from something that changed. The second phase of elaboration is to generate optimised simulation code for the design. This part can be slow, depending on your design, but we can spped it up easily by adding a switch "-mccodegen" to do the code generation in parallel.

The design topology analysis can't be parallelised, but we have a mechanism to allow you to partition the design into primary and secondary snapshots, where the the primary is part that doesn't change often (e.g. the DUT) and the secondary is the part that changes a lot (e.g. the TB). In this mode, you can avoid re-elaborating the primary part, thus saving a lot of time. Please check the tool documentation for "MSIE" or "Multi-Snapshot Incremental Elaboration" to see the use cases and corresponding switches.

To speed up elabration phase time Cadence recommends the Cadence's Multi Stage Incremental Elaboration (MSIE) flow. You can find Rapid Adaption Kit to adapt to this flow quickly.

Regards,

Sumeet.