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Set -access +rw for regression

PeterAF

I have an issue where forcing a value on a register works in simulator but not in regression

This is how it is done in the testcase.

uvm_hdl_deposit("tb_top.dut.infra_i.inst.gen_ing[0].inst.o_ing_pkt_cnt",32'hFFFFFFFF);

And the error I get in vManager for regression is

Attempting to place a value into tb_top.dut.infra_i.inst.gen_ing[0].inst.o_ing_pkt_cnt which does not have write access.

I found someone else on the internet that had a similar problem and solved it by setting -access +rw.

I need to know how to set this when running the regression. Should I set it in the testcase? In the vsif? Is it a setting in vManager?

  • This "attempting to place value" error is coming from the simulator, not from vManager.

    You will need to find where in your flow you are elaborating the design, and add the switches there. It's unlikely that your env would have been set up so that you add the switch directly in the VSIF, but it depends entirely on your flow, the tool doesn't control your flow.

    In any case, I would advise against using -access +rw, because it's a global switch that will hurt simulation performance. It would be better to work out which signals you need access to, then put them into a text file to use with the "-afile" option, documented here

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