How do I port a signal (reference data) from testbench to RTL module?

I don't really understand the intention here; if the signal doesn't already exist in the design, what's the point of creating a new signal with no connections inside the RTL?

If you really want to do this, perhaps the easiest way is to use a PSL vunit declaration, which in effect adds code in-line to the target module. Assuming that the module you want to add the signal to is called "target_mod", and the signal you want to create is "tb_data" (replace with your own names)... Create a file called target_mod.psl with the following content:

vunit (target_mod) {
  logic [31:0] tb_data;
}

Now, pass this to the compile + elab irun command using the option "-propfile_vlog target_mod.psl".

You can then use a traditional Verilog OOMR (out of module reference) or $nc_mirror() to reflect the TB signal into the RTL.

Thank you that seems working.