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Promote SVA failure to uvm_error

Ezequiel

How could the System Verilog Assertion failures be promoted to UVM_ERROR to be reported by the UVM environment?

I am aware that it can be coded as:

  assertion_name : assert property (
    // ...
  )
  else
    `uvm_error("SCOPE", "ERROR MESSAGE")

What I am looking for is to change the default behavior so the else is not needed:

  assertion_name : assert property (
    // ...
  )

Thanks,

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