run_phase doesn't update SV interface signals

Hi,

I am trying to set up a minimal UVM env to learn this methodology.

My problem is that UVM driver doesn't seem to update the interface signals connected to DUT. Testbench can update it (clock and reset are driven). Counter runs because clock and reset could be applied.However the driver does not seem to work, even the $display in run_phase is not called. I have doubt that driver is setup properly. I have neither compilation nor elab errors. 

Can anybody point me where my error is?

The example below is a derivative of the UVM example in Youtube film First Steps with UVM Part 2 by Doulos.

Shall I use modports in the interface?

Interface:

interface dut_if;
logic i_clk;
logic i_rst;
logic i_load_en;
logic [7:0] i_load_val;
logic [7:0] o_counter;
endinterface

DUT:

module my_counter (dut_if dif);

always_ff @(posedge dif.i_clk) begin
if (dif.i_rst)
dif.o_counter <= '0;
else if (dif.i_load_en)
dif.o_counter <= dif.i_load_val;
else
dif.o_counter <= dif.o_counter + 1;
end

endmodule

Testbench:

module tb ();

import uvm_pkg::*;
import my_pkg::*;

dut_if dif();

initial
begin
dif.i_clk = '0;
forever #10 dif.i_clk = ~dif.i_clk;
end

initial
begin
dit.i_rst = '1;
#15 dif.i_rst = '0;
end

my_counter dut (.dif (dif));

initial begin
`uvm_info ("SIM START", "Simulation has started!!", UVM_MEDIUM);
uvm_config_db #(virtual dut_if)::set(null, "*", "dut_if", dif);
uvm_top.finish_on_completion = 1;
run_test("my_test");
end

always @(posedge dif.i_clk)
begin
`uvm_info ("", $sformatf("DUT received %b", dif.o_counter), UVM_MEDIUM);
end

endmodule

UVM package:

package my_pkg;

import uvm_pkg::*;

class my_env extends uvm_env;
`uvm_component_utils (my_env)

function new (string name, uvm_component parent);
super.new(name, parent);
endfunction

endclass

class my_test extends uvm_test;

`uvm_component_utils (my_test)

my_env m_env;

function new (string name, uvm_component parent);
super.new (name, parent);
endfunction

function void build_phase(uvm_phase phase);
m_env = my_env::type_id::create("m_env", this);
endfunction

task run_phase(uvm_phase phase);
phase.raise_objection(this);
#200;
`uvm_info("", "Hello world", UVM_MEDIUM);
phase.drop_objection(this);
endtask

endclass: my_test

class my_driver extends uvm_driver;
`uvm_component_utils (my_driver)

virtual dut_if dut_vi;

function new(string name, uvm_component parent);
super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);
if (! uvm_config_db #(virtual dut_if)::get(this, "", "dut_if", dut_vi))
`uvm_error ("", "uvm_config_db::get failed");
endfunction

task run_phase(uvm_phase phase);
forever
begin
@(posedge dut_vi.i_clk);
$display ("run_phase!!");
dut_vi.i_load_en <= '0;
dut_vi.i_load_val <= $urandom;
end
endtask

endclass: my_driver
endpackage

Cadence version is 15.22.