Unable to simulate Verilog Testbench - 'lic_error-18'

Hi,

I am trying to simulate a simple AND gate written in Verilog, using NCLaunch.
The code for my gate is the following (andgate.v):

`timescale 1 ns / 1 ns
/* A simple AND gate
File: andgate.v              */

module andgate (a, b, y);
input a, b;
output y;

assign y = a & b;

endmodule

The code for my test bench is the following (andgate_tb.v):

`timescale 1 ns / 1 ns
/* testbench for AND gate
File: andgate_tb.v */

module andgate_tb;
wire t_y;
reg t_a, t_b;

andgate my_gate( .a(t_a), .b(t_b), .y(t_y) );
initial
begin

    $monitor(t_a, t_b, t_y);

    t_a = 1'b0;
    t_b = 1'b0;

    #5
    t_a = 1'b0;
    t_b = 1'b1;

    #5
    t_a = 1'b1;
    t_b = 1'b0;

    #5
    t_a = 1'b1;
    t_b = 1'b1;

end

endmodule

In NCLaunch, I manage to compile both the andgate.v and andgate_tb.v files without errors (using ncvlog). I also use the elaborator on my top file which is andgate_tb, in order to create the necessary snapshot.

Unfortunately when I choose the created snapshot and press the "Launch Simulator with current selection" button, the simulator fails to be invoked giving me the following error:

"ncsim: *F,NOLICN: Unable to checkout license for the simulation. Use ncsim -MESSAGES for more information. (flag - 2) 'lic_error -18'."

When I execute the "ncsim -MESSAGES" command, I get the following information:

" ncsim: *F,MISSIM: Missing simulation name."

Is this a license problem, meaning that I don't have the necessary licanse to run the simulator? This is strange as I am perfectly able to open without any problem the SimVision simulator.

Can you please provide me some help on how to simulate my test bench?

Thank you in advance for your feedback and help!

P.S.
I am following the guidelines in the NCLaunch User Guide (NCLaunch User Guide
Product Version 14.1 June 2014). I tried the same with the example tutorials that are provided by Cadence, but still I get the same error.