Create Functional Verilog from Schematic.

Hi,

I have a simple schematic with three same AND gates connected together. Each AND gate has also a functional view (obviously the same for all of them) , written in Verilog.
What I am trying to achieve is to create the functional Verilog from my  schematic  with the three AND gates connected.

The Functional view of my AND gate is the following:

`timescale 1ps/1fs
`define DLY 1.0

`celldefine
module ANDgate ( Z, VDD, VNW_N, VPW_P, VSS, A, B );
input A,B;
output Z;
inout VDD,VNW_N,VPW_P,VSS;

//instantiations of standard logic
and (temp_outZ,A,B);
assign Z = ((VDD === 1) && (VSS === 0))? temp_outZ : 1'bx;
//// Specify block section
specify

if(A==1'b1) (B => Z) = (`DLY,`DLY);
if(B==1'b1) (A => Z) = (`DLY,`DLY);

endspecify

endmodule
`endcelldefine

While I am in Virtuoso environment, inside my Schematic, I press Launch->Plugins->Simulation->NC-Verilog.
In the pop-up box, I press Initialize Design  and I get the following error:

ERROR (VLOGUI-18): Failed to start simulation. The NC-Verilog Executable field on the Simulation Setup form should not be left blank. Specify the NC-Verilog executable name and try again.

Then I am pressing the Generate Netlist option and I get the following errors:

INFO (VLOGNET-80): The library 'LIBRARY_AM', cell 'andTest', and view 'schematic' has been netlisted successfully.

ERROR (VLOGNET-177): Unable to check in license 21400. Specific error message follows

ERROR (LMF-04017): License call failed for feature 21400. The license server search path is defined as <none>. The FLEXnet error message is as follows,

FLEXnet ERROR(-17, 624, 32): Cannot write data to license server system.

Run 'lic_error LMF-04017' for more information.

End netlisting Jun 15 16:37:28 2018

ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all, or the generated netlist could be corrupt. Fix the reported errors and regenerate the netlist.


How can I create Functional Verilog for my top-cell from my Scheatic, when each of the sub-cells has its own Functional Verilog? Is it  a problem with my licenses that I am experiencing?

I am using NC-Verilog version 15.20-s052 and Virtuoso version ICADV 12.3.

Thank you in advance for your help and your feedback.

Kind regards,
Nassos