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Interface port coercion

int19

Hi,

I recently came across this two papers which would fit really well in our block and system level testbenches:

Verification prowess with uvm harness

UVM Harness

The idea is to declare all interface ports as inputs and, if anywhere in the testbench a certain port is driven to a value then the port is "coerced to inout" at compile time.
This feature is part of the SystemVerilog standard:

23.3.3.1 Port coercion
A port that is declared as input (output) but used as an output (input) or inout may be coerced to inout. If not
coerced to inout, a warning shall be issued.

It is a really interesting feature and become even more powerful when coupled with the bind statement.

However, when trying to compile some example code with irun I get this error:

A net is not a legal lvalue in this context [9.3.1(IEEE)]

So, it seems that irun doesn't support it (tried the same example code and it runs fine on other simulators).
Has anyone come across this issue before? Is there any magic switch that would enable it?

Regards
Mario.

Parents

  • Which version of the simulator are you using? Can you provide a runnable example as an attachment?

  • in reply to StephenH

    Hi Stephen,

    I am using version 15.20.028

    Below the example code I am running:

    interface block_if ( input wire a, input wire b );
endinterface

module myblock( input a, output b);
  assign b = ~a;
endmodule

module mytop (input a, output b);
  myblock u_block (.a (a), .b (b));
endmodule

interface block_harness();
  block_if intf( .a (myblock.a), .b (myblock.b));
endinterface

bind myblock block_harness harness();

class mytb;
  virtual block_if vif;
  function new (virtual block_if vif);
    this.vif = vif;
  endfunction: new

  task run();
    repeat (100)
    begin
      if (0)
        vif.a = $random;
      #10ns;
    end
  endtask
endclass: mytb

module tb();
  mytop u_top (.a(1'b0), .b ());

  initial begin
    mytb env = new (u_top.u_block.harness.intf);
    env.run();
    $finish();
  end
endmodule
Reply
  • in reply to StephenH

    Hi Stephen,

    I am using version 15.20.028

    Below the example code I am running:

    interface block_if ( input wire a, input wire b );
endinterface

module myblock( input a, output b);
  assign b = ~a;
endmodule

module mytop (input a, output b);
  myblock u_block (.a (a), .b (b));
endmodule

interface block_harness();
  block_if intf( .a (myblock.a), .b (myblock.b));
endinterface

bind myblock block_harness harness();

class mytb;
  virtual block_if vif;
  function new (virtual block_if vif);
    this.vif = vif;
  endfunction: new

  task run();
    repeat (100)
    begin
      if (0)
        vif.a = $random;
      #10ns;
    end
  endtask
endclass: mytb

module tb();
  mytop u_top (.a(1'b0), .b ());

  initial begin
    mytb env = new (u_top.u_block.harness.intf);
    env.run();
    $finish();
  end
endmodule
Children
  • in reply to int19

    Hi Mario,

    I have also based a uvm verification environment on the papers you have referred to. I have a gpio interface with ports being declared as input and the code simulates fine with VCS. However, the agent was not able to drive a signal into the dut which led me to believe that ports were not coerced. I added the -rnm_tech switch of xrun and it did it for me. I am running with xcellium 19.03.013.

    Regards,

    Omid.

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