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Replace "`includes" with in-line modules - NC-Verilog

anmos

Hi,

I am using the Virtuoso Verilog Enviroment (NC-Verilog), in order to generate the functional Verilog model of my top Schematic. For some of the components of my Schematic, I have written their functional models. In the tab Setups -> Netlist, I have selected the option "Single Netlist file". In the generated  Verilog netlist, the tools use "'include", to include the Verilog functional modules of the Schematic's components. I want to replace the "`include"s, with the Verilog modules inline. How can I achieve this automatically through the tools?

Kind regards,
anm

  • I managed to found the solution. In ncsim environment, after the compilation of the top Verilog netlist, I run the command

    ncdc -output ./mydc.v my_lib.top:snap

    and it generated a top Verilog file with all the "included" modules now inline. I am posting my answer in case someone finds it useful.

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