• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. Cadence Spectre Design Simulation

Stats

  • Locked Locked
  • Replies 0
  • Subscribers 65
  • Views 12952
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cadence Spectre Design Simulation

Hackasim
Hackasim over 6 years ago

Hello. I'm new to Spectre and Spice.
I've just created a .scs file, in which I have to write the testbench for the synthesized module inside the imported .v file.

include "library_path"

simulator lang = spice

.HDL "synthesized_module.v"


.END

My question right now is: how do I create that module in the .scs file?

Thank you in advance.

  • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information