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System Verilog Assertions

Manasy M

Hi all,

I have the following scenario for writing assertion.

Signal  'A' rises two cycles after 'B' falling. The high period of 'A' is, 70 + (var_value) clock cycles.

'var_value' is a variable

I wrote two assertions to check this scenario;

1. property A_RISE;
    @(posedge clk) 
    $fell(B) |-> ##2 $rose(A);                                                //to check the dependency of A w.r.t B
    endproperty

    ASSERT_A_RISE : assert property(A_RISE);

2. property A_HIGH_PERIOD;
    @(posedge clk)
     $rose(A) |-> A[*70] ##1 A[*var_value] ##1 !A;           //to check the high period of A;  ERROR: var_value must be a constant
    endproperty

    ASSERT_A_HIGH_PERIOD : assert property(A_HIGH_PERIOD);

Is there any better way to check both dependency and high period together?

How can we use variable cycle delays or sequence repetitions in assertion properties??

I have started to practice system verilog assertions recently only; Please provide me some guidelines to proceed with this.

Thanks

Parents Reply Children
  • in reply to StephenH

    Thank you for the advice. I will proceed in this way.

    How does the assertions affect simulation time?? Will multi thread assertions slow down the simulation time? If it does, what is the best way of writing assertions, which will avoid this problem?

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