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How to effectively browse verilog source in Cadence

Hi,

I know simvision can trace do source/load driver tracing but I believe it is more aimed at actual value tracing more than "browsing" through the code. I.e. I am looking for a Verdi style tracing, where it is easy to stop at module boundaries, the hierarchical panel on the left tells me where I am, etc. I find it really useful in seeing the bigger picture with regards as architecture, interconnections b/w modules and so on. In Simvision I just get lost when moving across boundaries, I could never find a way to make it work the way Verdi does. I am not sure I am using the right tool for the job?

Thanks

Andrew Beckett over 6 years ago

This is posted in the wrong place - the Feedback, Suggestions and Questions forum is for issues with the forums themselves, not for technical questions. I'll move this to a more suitable technology-specific forum where hopefully you'll get an answer.
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DonVerilog over 6 years ago in reply to Andrew Beckett

thanks Andrew, can you please provide me with the link to the new post ? Rgds
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Andrew Beckett over 6 years ago in reply to DonVerilog

It's not a new post - it's the same post, just moved into the right forum. Look at the top of the page, you'll see this is now in the Functional Verification forum. So you posted in the link for the right forum.

Andrew.
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