Stats

  • Locked Locked
  • Replies 0
  • Subscribers 64
  • Views 12999
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to effectively browse verilog source in Cadence

DonVerilog

Hi,

I know simvision can do source/load driver tracing but I believe it is more aimed at actual value tracing more than "browsing" through the code. I.e. I am looking for a Verdi style tracing, where it is easy to stop at module boundaries, the hierarchical panel on the left tells me where I am, etc. I find it really useful in seeing the bigger picture with regards as architecture, interconnections b/w modules and so on. In Simvision I just get lost when moving across boundaries, I could never find a way to make it work the way Verdi does. I am not sure I am using the right tool for the job?

Thanks

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.