i tried to deposit a value inside a register using this code:
$xm_deposit("tb_chip_top_s222.dut_u.i_digtoppad.i_dig_top_pads.i_dig_top.i_volt_cfg_regs.i_cfg_3_secded.\\secded_data_r_reg .Q", $sformatf("%b", cfg_3_secded_register_value));
This works in rtl simulation but i have some issues in gate level simulation where the deposit seems to behave like a force ( i see the D signal of the flip flop equal to 1 but it is not sampled after the posedge of the clock, maybe beacuse of the deposit on Q)
In the RTL sim, the internal state of the register is the same signal as the output of the register. So the deposit is overridden when the internal state is updated. Often in a synthesized model, the internal state of a flop is separated by one or more signals from the register's output. (The internal state may be a sequential UDP's "reg" variable.) Unless the deposit is changed to reference that internal signal, there can be times when the internal state change will not propagate to override the downstream deposit.
In version 17.10 of the simulator and later, there is an option -deposit_value_change which may override this behavior in your simulation. Give that a try and see if it works. If not, file a ticket with support.cadence.com and let them see how your gate-level register is modeled. The support AE's will be able to figure out what is happening.
Thanks for the response,
It does not seems to work..I will open a ticket as suggested.