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Design library not defined while reading module with ncsim

cuonghl

Hi supporters,

I got the following error while I run simulation with gate netlist using Cadence Incisive (v15.20):

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ncsim(64): 15.20-s076: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
ncsim: *E,DLOALB: Design library 'tcbnxxx' not defined while reading module tcbnxxx.MAOxxx:bv (VST).
ncsim: *F,NOSIMU: Errors initializing simulation 'alu_tb' 

----

xxx: standard library name.

My netlist design uses a cell "MAOxxx". I already included the library behavior model to compile using ncverilog, there is no error while compiling. But when I run with ncsim to execute the test, I got above error.

I tried to run with other vendors such as VCS or MTI, they worked.

 

Please help to understand the error.

Thanks.

  • It looks like you are using a legacy workflow with Incisive, where you defined a cds.lib and hdl.var file, and invoked the ncvlog, ncelab and ncsim directly. The error message comes because the compiled design refers to a Verilog (or VHDL) library name that wasn't listed in your cds.lib file. I would guess that you used a valid cds.lib when compiling the design but that you're simulating in a different directory where you either have no cds.lib, or the wrong cds.lib.

  • in reply to StephenH

    Actually, I don't touch the cds.lib. Here is the follow that I used (it worked when I run simulation using RTL):

    - Compile: ncverilog -64bit -clean -elaborate -access +wr -uvm -uvmhome $(UVM_HOME) -sv +nccoverage+A +nccov_cgsample +nctimescale+1ns/1ns -f $(LIST)

    - Simulation: ncsim -64bit -covoverwrite -sv_lib $(DPI_LIB) -svseed $(SEED) -log simulate.log $(TOP) +UVM_TESTNAME=$(TEST)

    It happened when I retried to bring up GLS, the netlist use some library macro model.

    Maybe I missed something, can you help guide me?

    Here is the content of "INCA_libs/irun.lnx8664.15.20.nc/cds.lib":

    1 include ./cdsrun.lib  

    2 include ./xllibs/cds.lib

    Then I checked the "xlibs/cds.lib" and I saw the library definition:

    define tcbnxxx ./tcbnxxx

    Thanks.

  • in reply to cuonghl

    Thanks for the clarification. So, the cds.lib does look ok, which leads to the question, did you compile anything into your tcbnxxx library? Does the ./tcbnxxx directory even exist? You could check by doing the command "ncls -library tcbxxx"; it should list all the compiled Verilog objects from the library, so if it reports nothing, or if it reports that it can't find the library, that is your problem.

  • in reply to StephenH

    I found that library was compiled OK. However the "ncsim" command couldn't load the "cds.lib" and "hdl.var", that's why the error happened.

    When I provide the options in "ncsim" command to specify the cds.lib and hdl.var. It works.

    ncsim -cdslib INCA_libs/snap.nc/cds.lib -hdlvar INCA_libs/snap.nc/hdl.var -64bit -covoverwrite -sv_lib $(DPI_LIB) -svseed $(SEED) -log simulate.log $(TOP) +UVM_TESTNAME=$(TEST) 

    I'm not sure why ncsim could not load cds.lib and hdl.var automatically? 

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