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Can Cadence Incisive Enterprise Verifier be used for functional verification?

Archana P

I understand that Cadence Incisive Enterprise Verifier is for Assertion Based Verification, it has within it Incisive Enterprise Simulator which lets the tool generate testbench stimulus from assertions and thus gives dual benefit of formal and functional verification. My doubt is if I can use the tool exclusively for functional verification? That is I have a set of test benches that are already written, and I need to just simulate it just like we do in modelsim. Is it possible to do in Incisive Enterprise Verifier? If possible, please give insights on where I can refer on how to do that. I can't find details on this topic in the manual or user guide.

  • IEV is a legacy tool for formal property checking. You're right that it does include the IES simulator component as well to allow you to simulate regular behavioural testbenches as well, but IEV's primary role is for property checking.

    If you're struggling to find information on this, login to support.cadence.com and look for the Incisive Enterprise Simulator 15.20 User Guide. You should find it under the Resources -> Product Manuals drop-down menu at the top of the screen. If you've already got a simulation environment for Modelsim, then it should be fairly simple to take the same set of source files and pass them to the "run" command for Incisive. Run is a front-end for compiling and simulating the code. Some options will be common, but if you have any Modelsim switches that are proprietary to Modelsim, you'll need to look at the iron user guide to understand how to convert those to something compatible with Incisive. Your local Cadence AE can help with that, if you need help.

    Note that Incisive is a legacy tool, it was replaced by Xcelium in 2016, and Cadence can only provide very limited support for Incisive now, so if you have the option, please try to use Xcelium.

  • For functional verification one should access incisive enterprise simulator;

    irun -access +rwc -gui -simvisargs "-waves" design.v tb.v

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