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generate over a loop the same module with different parameter and maintain it in systemverilog UVM environment

EranW

Hi,

I've encountered in an issue that I'm trying to generate an interface with different parameter (DW) over a loop.

Therfore, I found that I've two problems;

1. How to generate the block (interface in my case) with a different parameter  (between each interface) over a loop?  I've tried generate block. 

2. How to maintain the data through config_db (set and get), virtual_interfaces, agents - same type with different parameters over the environment?

In case I've a chain of passive agents I don't like to duplicate the code so many times in my environment.

Regards,

Tomer

  • Parameters in classes are somewhat viral; once they get in, they tend to replicate very fast and end up everywhere!

    If you have a limited number of values needed for DW, you could consider using a typedef for each one, to simplify the code, but that won't help for the interface instances.

    I'm not sure how you intend to derive the DWW value for each interface - is it calculated somewhere? Is the number of interfaces known in advance? How do you plan to bind the interface signals / ports if the signals aren't statically known?

  • in reply to StephenH

    Hi,

    Thanks for your help.

    Regarding your question, I know the DataWidth (DW) per each interface/agent/monitor/item - You can think about it as a chain of checkers. Therefore, I know these numbers and they won't be changed for the entire project. It's not calculated and shouldn't be neither.

    The number of the interfaces is known.

    Currently, it runs well, but I duplicated the code per each interface/agent/monitor/item/scoreboard/environment - It's not nice at all to duplicate the code so many times.

    Actually, I didn't find how to create all the components over loop in a kindly way.

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