SystemVerilog EEnet input driven by current source

Hi,

I am using the Cadence System Verilog EEnet package to model analog ports.

I am running the simulation in the Virtuoso (6.1.8) environment. 

I do have a problem with input ports defined as EEnet and driven by a Spectre current source (analogLib->icd).

What I did:

1. Modelled a resistor (100R) in SystemVerilog with port "P" as an input with EEnet datataype.

2. Create a schematic with an ideal current source (100uA) connected to the EEnet input.

3. Defined in the test the following interface element: Setup-->ConnectRules/IEsetup 

    instport | /I0/P | ……  (advanced Setup  current mode=1)

I expect to get the EEnet input current value "P.I" = 100u, but it is not the case, it always gives back 0.

The node voltage "P.V" is solved correctly. 

I basically want to check in the SystemVerilog model if the input current is in the correct range and if not, I want to output an assertion.

How can I do that ?

[Edit:] 

I understand that the node current "P.I" is always resolved to 0, due to Kirchhoffs law. 

That would basically mean that the input port must be given a fixed resistance "Rval=100" and "P.R=Rval" and the node current is calculated as "P.V/Rval"  (the calculation P.V/P.R will result in false numbers, because P.R will change during simulation and result in another value - don't know why).

I also found that the "current mode" in the Setup->ConnectRules/IE setup is not required in this case !

Are there other approaches to check an input current into an EEnet and evaluate the current into this node directly ?