Hello All I want to cross-coverage between two different covergroup, Is it possible to do this? Does the Cadence tool have this feature?`
This isn't permitted by SystemVerilog, because the two covergroups could be sampled at different times / events, meaning that it's impossible to know what the cross actually means (i.e. when the coverpoints are sampled and when is the cross sampled).
You'll need to put your coverpoints inside the same covergroup in order to define the cross.