I'm trying to run a behavioral simulation of my Verilog design, but somehow the Xmsim simulator seems to go into an infinite loop and the simulation stops advancing. It literally gets stuck. I was wondering if there is a way to view what line of Verilog code is being evaluated/executed at the time. Is this possible with Xmsim HDL simulator?
Thanks in advance.
Yes, but you need to compile the design with -linedebug, then once the sim is stuck you can do Ctrl-C and it'll interrupt the simulation and tell you what line it's on.
Often the hang is caused by a clock toggling with zero delay due to rounding errors with time precision, however there are many other possible causes.
We have a good application note describing how to debug stuck simulations: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTGDEA2&pageName=ArticleContent
That worked. Thanks a lot Stephen.