convert bus sıgnal

Hello, my output is 3 bit. It shows range of -4 and 3, naturally as a sıgned. But  output of error cancellation network shows between -3 and +4 in result of noise cancellation with adder and substractor. I want to convert -4 to +4 or means that converting signed 100 to unsigned. How can I do it?.

I try to it with mux, converting 3 bit to 4 bits. But  while half of them signed adding 1, other half unsigned adding 0. It is diffucult because I can not make out<3> bit both 1 or 0. Another solution,may be verilogA. BUT ı failure to write it  as below. Can u help me please?   

`include "constants.vams"
`include "disciplines.vams"

module dec (input [2:0] x, output [3:0] y);
wire [2:0] x;
reg [3:0] y;

always @(*) begin

case (x)

3'b001: y <= {1'b0,x};
3'b010: y <= {1'b0,x};
3'b011: y <= {1'b0,x};
3'b100: y <= {1'b0,x};
3'b101: y <= {1'b1,x};
3'b110: y <= {1'b1,x};
3'b111: y <= {1'b1,x};
endcase
end
endmodule