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Running SVA for a VHDL design (binding method)

My design is in VHDL so, my top file is ../VHDL/top.vhd
As it is now, the testbenches simulation do run fine. These are written in (System)Verilog.

How can I use the approach of SVA binding, to run an assertion file for a specific subcomponent on which I am interested in?!?
The component is comp1.vhd
The SystemVerilog Assertions (SVA) file for this component is comp1_sva.sv

I also have created the comp1_bind.txt, the binding file
with the generic structure inside

bind (design_module_name/design_instance_name) {sva_module_name}{bind_instance_name}(port_list);

The goal is to execute something like

xrun -assert -extbind comp1_bind.txt comp1.vhd comp1_sva.sv

Questions:
1. is the approach correct, in order to test a VHDL-design using SystemVerilog Assertions?
2. how to write exactly the comp1_bind.txt

NOTE: using above all the commands and guidance as found in the Xcelium help/tutorials/example files in the paths
<xcelium_install_dir>/doc/abvquickstart/...
<xcelium_install_dir>/doc/abvsimulate/...

NOTE2: for now, I only want to run this simulation (or testbench, whatever the naming is) for this component only, not the whole design.

Thanks for any advice!

quantumion over 4 years ago

Hi! Any hints on the above question?
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StephenH over 4 years ago in reply to quantumion

From the docs: https://support.cadence.com/apex/techpubDocViewerPage?xmlName=abvwrite.xml&title=Assertion%20Writing%20Guide%20--%20Using%20SVA%20-%20%20SystemVerilog-to-VHDL%20Binding%20Example%20&hash=UsingSVA-1041737SystemVerilog-to-VHDLBindingExample&c_version=21.03&path=abvwrite/abvwrite21.03/Using_SVA.html#UsingSVA-1041737SystemVerilog-to-VHDLBindingExample

SystemVerilog-to-VHDL Binding Example

The following example shows how a SystemVerilog assertion module can be bound to a VHDL entity/architecture.

The following bind statements are valid for this example:

  // Instantiates fifo_full in all instances of fifo.
bind fifo fifo_full v1(clk, empty, full);

   // Binds to an instance.
bind fifo:fifo1 fifo_full v2();

   // Binds to an instance.
bind cell(v2_arch) fifo_full v3();

Note: Do not specify the entity/architecture using a hierarchical name starting with a Verilog top. Verilog hierarchical names ending in VHDL scopes are not permitted.

With reference to your comment "I only want to run this simulation (or testbench, whatever the naming is) for this component only, not the whole design" - this sounds like you should look at the capture-replay technology in Xcelium: Debug Design Effectively Using Xcelium Capture-Replay Feature
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Running SVA for a VHDL design (binding method)

SystemVerilog-to-VHDL Binding Example

Community Guidelines