Running "small environment" on specview

The philosophy around clocks in Specman was that it's more efficient to generate them in the HDL simulator and have Specman components as slaves to that clock, it's more performant that way. It also avoids the complexity of having to build a separate timing engine inside the Specman core - delays are simply sent to the simulator for processing. This is why you see the warning about @sim and delay statements not being honoured.

The simplest way to get running would be to write a tiny SV harness to generate a clock:

module tb;
bit clk;
always #1 clk = ~clk;
endmodule

compile that with "xrun tb.sv -snload top.e" (assuming you called your top Specman file top.e) and off you go.

The more complex way to make a stand-alone Specman testbench is to redefine the clocking events for the components,using a special pattern for standalone mode.

You'll want to reference the docs here: https://support.cadence.com/apex/techpubDocViewerPage?xmlName=sn_run.xml&title=Compiling,%20Linking,%20and%20Running%20Specman%20--%20Running%20Specman%20Standalone%20-%20Running%20Specman%20Standalone&hash=&c_version=21.09&path=sn_run/sn_run21.09/Running_Specman_Standalone.html 
but I've pasted the most relevant part for you here, for convenience.

2.3. Defining a Clock for Standalone Specman

To exercise and debug the TCMs in your e code without a simulator, you probably also need to define a standalone clock.

In standalone Specman operation (that is, with no simulator attached), the sys.any event is the only one that occurs automatically. It typically is used as the clock for standalone operation.

For example, you may have defined the clock that drives the system when linked with a simulator as follows:

<'
extend sys {
  event clk is rise('top.clk')@sim; // clk drives the system
};
'>

In this case, you need to use extend to override the clock to tie it to sys.any for standalone operation.

<'
extend sys {
  event clk is only cycle @sys.any;
};
'>

If the TCM you want to exercise waits on other signals from the DUT, such as:

wait until rise('~/top/cpu/s_fetch1')@clk;

You will also need to set those signals to appropriate values.

Thank you for the respawn,

I did create the tb file as you mentioned and I wrote a the e code. I'm still encountering the same issue (RR_TE_NOSIM: No simulator is attached) and I wanted to ask if the problem is using the specview instead of different environment, if not, can you direct to my mistake in the code?

This is the code I wrote:

<'

unit clock_driver {
    clk: inout simple_port of bit is instance;
    keep bind (clk, external);
    keep soft clk.hdl_path() == "clk";

};

extend sys {
// creating the connection to the tb
    clock_driver_i: clock_driver is instance;
    keep clock_driver_i.hdl_path() == "~/tb";

// event for
    event clk is rise(clock_driver_i.clk$)@sim;

// TCM for test.
    tcm_test() @clk is {
        print sys.time;
        wait [10]*cycle;
        print sys.time;
    };

    run() is also {
        print ("start run");
        start tcm_test();
    };
};

'>

Thanks a lot,

Nir

What command are you using to launch the tool?

The xrun command that I gave you should work fine, and you can get GUI mode by simply adding -gui to that command.

My recollection was that specview was deprecated some years ago, in favour of the native integration of Specman into the SimVision GUI. I honestly can't remember the last time I ran specview! :-/

I checked it again and it does work with the simvision gui, thank you!