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Passing variables between structs and sequences

Nir Z

Hi all,

I'm Trying to create an effective "end of test" condition where I generate packets in a designed unit and send them to a sequence.

I'm interested that after a X amount of packets the sequence will end. The problem is that the "number of packets" generated in the designed block is defined there and I'm not sure what is best way to make it visible to my sequence so I could have the "end of test" condition.

Important to mention that I'm working on a big based environment and I'm trying not to make to much changes.

Thank you for your help,

Nir

Parents

  • Why not simply add an attribute into the transaction class to signal the end of the stream? Then set it to 1 in the last transaction sent from the packet generator, and in your sequence, break out of the loop when the flag is set.

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  • Why not simply add an attribute into the transaction class to signal the end of the stream? Then set it to 1 in the last transaction sent from the packet generator, and in your sequence, break out of the loop when the flag is set.

Children
  • in reply to StephenH

    I could do it, and probably will, but because my code is part of big environment with many module (and I'm working on a small side module) my transactions are defined as well in many other environments who uses the same transaction definition.

    Is there any other way of passing those variables without changing the transaction class?

  • in reply to Nir Z

    Well, given that you haven't even said which language you're using (e, SV, UVM, SystemC, raw VHDL...) it's kinda tricky to propose anything precise. I'm going to assume you're using SV UVM, in the which case you could consider making a derived transaction class that adds the flag, then use a factory override so that you can make the changes only for your use case and not for everyone else.

    You might be able to do something really dirty like making a hierarchical reference from the sequence across to the packet generator, but then your code will be harder to maintain, more fragile and less reusable.

    It's also not clear why your packet generator isn't a sequence itself, that would be the normal use model in UVM.

    Perhaps the least intrusive method would be to make no changes to the transaction class or the generator, and instead simply add a mechanism in the sequence whereby it times out and terminates if it hasn't received any new packets from the generator after a defined number of clock cycles...

  • in reply to StephenH

    Thank you for your help,

    I'm Working with e language. In the end I added an attribute into the transaction class like you offered and it was the simplest solution.

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