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Why xrun timescale does not comply with SV-2012 spec?

galenxiao

In SystemVerilog 1800-2012 spec Section 3.14.2.3, there is below content:

" The time unit of the compilation-unit scope can only be set by a timeunit declaration, not a `timescale directive. If it is not specified, then the default time unit shall be used. "

But I run a simulation with xrun and find that `timescale effect timescale of compilation-unit scope. Please check below code:

----------------------------------------------------------------------------------


`timescale 1ns/10ps

class trans;

task add_delay;
$printtimescale;
$display("%t: add_delay begin",$realtime);
#2.123;
$display("%t: add_delay end",$realtime);
endtask

endclass


`timescale 1ps/1ps
module tb_top;

trans tr;

initial begin
tr = new;
$timeformat(-9,3, " ns", 15);
$printtimescale;
tr.add_delay;

end

endmodule

-------------------------------------------------------------------------------

I save this code as file tb_top.sv, and run command:  xrun tb_top.sv

Then, below info print:

Time scale of (tb_top) is 1ps / 1ps
Time scale of (worklib.$unit_0x35beeaed::trans) is 1ns / 10ps
0.000 ns: add_delay begin
2.120 ns: add_delay end
xmsim: *W,RNQUIE: Simulation is complete.

In my opinion, class trans should have timescale of 1ps/1ps, which is same to tb_top.sv. The first timescale(1ns/10ps) should not take effect.

I've tried Synopsys VCS, it print below info:

TimeScale of tb_top is 1 ps / 1 ps
TimeScale of $unit is 1 ps / 1 ps
0.000 ns: add_delay begin
0.002 ns: add_delay end

This is what I expected, I think VCS works well.

Does anyone know why xrun does not comply with SV spec?

Thanks!

  • Well, it's probably a limitation of the SV parser; every EDA tool that reads SV has limitations or non-compliances.

    It is generally considered to be very bad practice to use the compilation unit scope for making any declarations, because it makes your code sensitive to compilation order and can lead to inconsistent results depending whether someone compiles each file individually or everything in one command. Worse, it also creates false dependencies between files, which makes incremental build processes less efficient.

    Wrap everything in packages or modules and never declare types or classes outside of a package or module.

  • in reply to StephenH

    It's also worth noting that IEEE1364-2001 Verilog does not say that `timescale doesn't apply to compilation unit scope, perhaps because there was no way to declare anything outside of a module in Verilog. The Xcelium parser of course originated with Verilog-XL (when Cadence Verilog-XL was the actual standard before the IEEE standardisation of Verilog), so there will inevitably be some "baggage" left over where certain rules in the parser haven't been re-implemented for the later SV versions.

  • in reply to StephenH

    Thank you, StephenH. I will follow your advice, use package to incorporate class definition Slight smile

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