[Doubt when initializing memory in netlist file]

Hello, I have a problem with my verification process in which I couldn't find a solution to get around my problem.
I apologize, but I'm relatively new to this process.

In the study project I'm working on, I use a verilog testbench to perform my simulations with the xcelium simulator, for that, I make some hierarchical accesses of the instances contained in my submodules used in my testbench, for example:

In my "my_top_level", there is a kind of RAM, defined as:

 reg[31:0] RAM [0:100];

so i populate my ram with data via testbench doing:

module testbench;

 my_top_level my_top();
 reg [31:0] RAM_x [0:100];
 $readmemh("test.hex", RAM_x);
 for (i = 0; i < `L_RAM; i = i + 1)
   testbench.my_top.RAM[i] = RAM_x[i];

....

Worked well for my purpose. Also, I do this type of access to initialize some values to be able to run my simulation normally.

Example: testbench.my_top.processor.cycles = 0;

but when generating the netlist file there is something like:
  wire [31:0] \RAM[1] ;
  wire [31:0] \RAM[4] ;
  wire [31:0] \RAM[0] ;

Currently, I want to go ahead with a port-level simulation.
Because previously, I was making use of the non-synthesized "readmeh" instruction to be able to initialize my memory with my test instructions.

And I have no idea how to handle this kind of situation with the memory now unpacked. Would anyone have a direction on how to go about this? I'm very grateful!