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  3. UVM constraint randomization doesn't work

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UVM constraint randomization doesn't work

Ketrin
Ketrin over 2 years ago

Hi, I wrote verification code (here two classes which extend from uvm_sequence_item and uvm_sequence). The $display in sequence illustrates only "ITEM: 000000000000000000000 or 0000000000000000" for 7 times (not 8). 


class item_incode extends uvm_sequence_item;
`uvm_object_utils(item_incode)
bit [20 : 0] in_code;
bit signed [15 : 0] in_data;

virtual function string convert2str();
return $sformatf("in_code = %b, in_data = %b", in_code, in_data);
endfunction

function new(string name = "item_incode");
super.new(name);
endfunction

constraint c_incode {
0 <= in_code [20 -: 3]; 3 >= in_code [20 -: 3];
0 <= in_code [17 -: 6]; 64 > in_code [17 -: 6];
0 <= in_code [11 -: 6]; 64 > in_code [11 -: 6];
0 <= in_code [5 -: 6]; 64 > in_code [5 -:6];
}
constraint c_indata {in_data inside {[-32767:32767]};}

endclass

class seq0 extends uvm_sequence # (item_incode);

`uvm_object_utils (seq0)

function new(string name = "seq0");
super.new(name);
endfunction

virtual task body();
repeat (8) begin
item_incode incode = item_incode::type_id::create("incode");;
start_item (incode);
incode.randomize();
$display("ITEM: %b or %b", incode.in_code, incode.in_data);
`uvm_info("SEQ", $sformatf("Generate new item: %s", incode.convert2str()), UVM_HIGH)
finish_item(incode);
end
`uvm_info("SEQ", $sformatf("Done generation of items"), UVM_LOW)
endtask

endclass

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  • Ketrin
    Ketrin over 2 years ago

    The questions are why incode.randomize() doesn't work and why "ITEM: 000000000000000000000 or 0000000000000000" is displayed only 7 times?

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  • Ketrin
    Ketrin over 2 years ago

    The questions are why incode.randomize() doesn't work and why "ITEM: 000000000000000000000 or 0000000000000000" is displayed only 7 times?

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  • StephenH
    StephenH over 2 years ago in reply to Ketrin

    You need to declare which class members are to be randomized, using the "rand" keyword.

    Cadence offers free online SystemVerilog and UVM training, perhaps you would like to try it out? Point your web browser at https://support.cadence.com/ and once registered / logged in, go to the "Learning" link to access the courses.

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  • Ketrin
    Ketrin over 2 years ago in reply to StephenH

    I actually did the same thing as in the example: SystemVerilog Randomization (chipverify.com)
    There was no need to declare exact class members, only [name_object_of_class]..randomize();
    Perhaps I misunderstood you and you proposed another solution

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  • StephenH
    StephenH over 2 years ago in reply to Ketrin

    SV requires you to use the "rand"qualifier for class member variables that are to be randomised. Failure to declare as "rand" means that the variables are state variables and won't get random values. This is really basic SV stuff. Your declarations should look like:

    rand bit [20 : 0] in_code;
    rand bit signed [15 : 0] in_data;

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