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unable to simulate VHDL record constant assignment through component port

Hunen

Hey,

I am not sure if this is the right board, kindly move it to the right one.

When trying to simulate the attached test-case using Xcelium, I am facing below error as can be seen in the snapshot below:

The same code simulates in Questa but the constant should have a value of 8 instead it has 0x8000_0000, (-2147483648). The code seems valid to me, kindly share your thoughts what could be done to simulate it?

Thanks,

Hu

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  • StephenH

    I think you meant to post this on the Synopsys support site. Although you mention Xcelium in your text, the screenshot shows a Synopsys VCS compiler error, and much as I love to help my customers, I would not be allowed to help debug issues with a competitor's tools Slight smile

  • Hunen
    in reply to StephenH

    Hey,

    Apologies for the inconvenience. I was trying on couple of simulators and had posted the VCS error snap, I have edited my message to have the Xcelium error. Hence, let me know what could be the issue here? 

    Appreciate your help

    Thanks,

    Hu

  • tpylant
    in reply to Hunen

    It looks like this issue has been fixed in 22.03-s004.

Reply
  • tpylant
    in reply to Hunen

    It looks like this issue has been fixed in 22.03-s004.

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