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  3. xcellium compiles every RTL hierarchy into a "library_cell...

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xcellium compiles every RTL hierarchy into a "library_cell", how do I get rid of that?

mxlusereight
mxlusereight over 2 years ago

Hi Cadence, 

I use a vendor provided makefile (really huge) with ncsim simulation. 

In the GUI I can see an extra "Library Cells" hierarchy is added to every RTL file. While I compile the same RTL in my own scripts, I won't see that Library Cells hierarchy. 

That hierarchy is not wrong but navigating requires double the effort. I suspect some flags/+OPT are used but what is that flag?

I knew only when a standard cell or analog model is used, that Library Cells is added. 

Thank you!

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  • StephenH
    StephenH over 2 years ago

    Compiling a Verilog / SystemVerilog file using either the -v or -y switches tells the compiler that these files contain library cells, and the tool treats each module in the file as if it had a `celldefine macro around the module. This is so that huge gate cell libraries can be "hidden" in the GUI to reduce clutter as well as not enable things like code coverage by default on library cells.

    Your vendor's Makefile probably uses -y or -v to compile that files, whilst you're probably passing the file names explicitly on your compile command.

    There is an option you can add: -nolibcell, and this tells the compiler not to tag -y or -v files as library cells. Just insert that into your Makefile and you should see an improvement.

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  • mxlusereight
    mxlusereight over 2 years ago in reply to StephenH

    Thank you very much. The -nolibcell works. 

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