System Verilog: always @( * ) is not working, but explicit declaration always @( s1, s1, s3) is working

Could the problem be, that I do have multiple "always @( * )" blocks inside this module ?

Because I do have another condition and 'ifdef condition in the functional part of the module - below is the complete module code.

This code uses 'ifdef conditions to allow SV-RNM-bidirectional nets to be run in XCELIUM as well as in Synopsys VCS (just FYI):

//systemVerilog HDL for "CROCODILE", "atb_tiomux_tgate" "systemVerilog"

import CONTI_SV_PACKAGE::*;

`ifdef XCELIUM
import cds_rnm_pkg::*; //for Cadence tool-chain
`elsif VCS
import snps_msv_nettype_pkg::*;//for Synopsys tool-chain
`endif

`define T wreal4state //nettype to resolve net value

module atb_tiomux_tgate ( TG_out, VSS, ATB_TG_EN, ATB_TG_EN_B, TG_in );

inout `T TG_in;
input logic ATB_TG_EN;
inout `T TG_out;
input logic ATB_TG_EN_B;
input `T VSS;

//checking supply
`ifdef SUPPLYCHKOFF
logic supplyOk = 1;
`else
logic supplyOk = 0;
//always @( ATB_TG_EN, ATB_TG_EN_B, VSS, TG_in ) begin
always @( * ) begin
$display("TIO MUX GATE always block was triggered");
//range check
if( VSS inside {[minGND : maxGND]}) supplyOk = 1;
else supplyOk = 0;
end
`endif

//internal control logic
bit control;
assign control = ( (ATB_TG_EN && ~ATB_TG_EN_B) === 1'b1 && supplyOk==1 ) ? 1'b1 : 1'b0; //case comparison resolves to 0 if 'X or 'Z

`ifdef XCELIUM
//internal nets to store the external resolved value
`T TG_in_i = `wrealZState; //this initial value is essential for proper function
`T TG_out_i = `wrealZState;

// bidirectional functionality
assign TG_in = ( control==1'b1) ? TG_out_i : `wrealZState ;
assign TG_out = ( control==1'b1) ? TG_in_i : `wrealZState ;

//on a change, check the sense the external driver status
always @( * ) begin
$cged(TG_in, TG_in_i); //store outside resolved value on internal net
$cged(TG_out, TG_out_i);
end

`elsif VCS
tranif1(TG_in, TG_out, control);
`endif

endmodule

Since you seem to be using SystemVerilog, please replace the always @(*) with always_comb. The semantics of the always @(*) are not well defined and can cause incompatible resutls where different vendors have implemented the feature differently due to differing interpretations of the spec. always_comb is much more precisely specified in the SV standard and should be more portable.

Thanks Stephen for this hint - I will have a look and try to understand and use this is future in system verilog.

BUT the real issue is that I missunderstood the "always @ (*)" functionality.

So far (in my short verilog modelling career) had the understanding that the "*" means "ALL INPUTS IN THE MODULE"  - but it acutally means "ALL INPUTS INSIDE THE ALWAYS BLOCK" - which is a completely different functionality.

I now changed my code which will assign the "supplyOk" continously as combinatorial logic - do you see any issues with such a implementation - compared to the above approach with "always..." :

module atb_tiomux_tgate ( TG_out, VSS, ATB_TG_EN, ATB_TG_EN_B, TG_in );

inout `T TG_in;
input logic ATB_TG_EN;
inout `T TG_out;
input logic ATB_TG_EN_B;
input `T VSS;

//checking supply
`ifdef SUPPLYCHKOFF
   logic supplyOk = 1;
`else
   logic supplyOk;
   assign supplyOk = VSS inside {[minGND : maxGND]};
`endif

Yes, your new understanding is correct -- the always @(*) or always_comb refers to all signals on the RHS of expressions inside the always procedural block. The big difference between @(*) and comb is that always_comb executes at time 0 regardless of the signal values whereas always@(*) waits until there is a signal change before executing for the first time.

The code changes you made should provide the simplest solution for the functionality that you want.

Tim

Thanks for confirmation.

As I try to understand the differences between "always_comb / _latch /_ff" I think the differences among those functions are only relevant when the code will be synthesized - and it will give error if it cannot be synthesized as declared by either _comb / _ff or _latch.

In my case, I am doing AMS modelling and verification/testbenches only an do not care about synthesizability of the module.  Thus can I still use the "always  @*" function and by that avoid any error which might be caused due to non-synthesizability ?

Or does would this cause other issues ?

I indeed see the advantage of the initial execution of the new "always_comb/latch/ff" function.