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*E,CUVUNF - Hierarchical name component lookup failed

dasheksh

Hi,

I have a for generate loop(named for block) - which instantiates modules 2 times, something like this

generate 

for() begin : acc

//module instance 

//I have to make a connection to make which is coming as an out of inst0 to inst1

end

endgenerate

//so I was trying to connect like this

//assign acc[0].inst.a = var[0];

//assign acc[1].inst.a = out[0]; // This comes as an output from acc[0].insta.out

But I come across the above mentioned error - If anyone could answer could be helpful.

Thanks in Advance

  • I'm unsure what you're trying to do with the assigns. However, this code does work without error:

    module inst;
      logic a;
    endmodule

    module test;
    generate
      genvar i;
      for(i=0; i<2; i++) begin : acc
        inst inst ();
      end
    endgenerate

    assign acc[0].inst.a = acc[1].inst.a;
    //assign acc[1].inst.a = out[0]; // This comes as an output from acc[0].insta.out

    endmodule

    Tim

  • in reply to tpylant

    Thanks for the reply  

    what if we have to access a port list

    module inst(a,b);

    input logic a;

    output logic b;

    endmodule

  • in reply to dasheksh

    Did you try it? I didn't have a problem.

    module inst(input a, output b);
    endmodule

    module test;
    wire [1:0] in, out;

    generate
    genvar i;
      for(i=0; i<2; i++) begin : acc
        inst inst (in[i], out[i]);
      end
    endgenerate

    assign acc[0].inst.b = acc[1].inst.a;
    assign acc[1].inst.b = acc[0].inst.a;

    endmodule

    Tim

  • in reply to tpylant

    Hi Tim,

    I see, Somehow I see a problem at my end when I try to access variable inside port list.

    Let me deep dive more. As of now I used a workaround to move forward.

    -Shek

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