Stats

  • Replies 3
  • Subscribers 65
  • Views 2443
  • Members are here 0

How to eliminate DLCSMD errors in Xcelium's xrun

Celluk

Hello,

I am using cocotb in python to simulate SystemVerilog files and while there is no issue with other simulators such as modelsim, I came accross DLCSMD error in xrun. I have looked previous similar questions and I know that one can eliminate by changing the source with such as ifdefs however I have a lot of submodules that I cannot change the internal codes (that is not practical also) and I also want to override if there are duplicate codes. For example, in terms of modelsim's behaviour it overrides the same packages, however as can be seen below xrun cannot override them:

xmvlog: *E,DLCSMD: Dependent checksum verilog_package top.cva6_config_pkg:sv (VST) doesn't match with
the checksum that's in the header of: verilog_package top.ariane_axi:sv (VST).
import ariane_axi::*;
|

I thought another solution can be giving a clean file list however this is also not practical for me for such a big project. Getting them by recursively and override duplicates is better for me. I want to eliminate this error by giving a flag to xrun if possible. I thought this possible flag can be about disabling checksum control or enabling overrides for duplicate files-packages however I couldn't find a flag for my needs.

In short, is it possible to disable this error because it is not an actual error for me?

Parents

  • Here's the help message from 'xmhelp xmvlog DLCSMD':

    > xmhelp xmvlog DLCSMD

    xmhelp(64): 25.04-a072: (c) Copyright 1995-2025 Cadence Design Systems, Inc.

    xmvlog/DLCSMD =

    The contents of the specified intermediate file failed a checksum test. Checksums are generated and stored in the header of a dependent intermediate file during a particular operation, as an e.g. xmvhdl. Subsequent reads of the intermediate file (as an e.g. xmelab) will generate the checksum and will verify that the data read (through xmelab) matches the data used earlier (through xmvhdl) by comparing these checksums. 

    The checksum of an intermediate file between two read operations could be different due to the following reasons.

    1) File(text) contents are different between two read operations. 

    This could be due to the fact that two design units with different contents but with the same name have been compiled in the same library. This will result in overwriting of one design unit by another and NC-Tool will generate this error on any further operation on the design unit. (please go through LRM section 11.1 for more details)

    2) Intermediate file has been recompiled but with different arguments between two read operations. 

    3) Corrupt Intermediate file.

    The probable solution to avoid the checksum mismatch is to use, "-update" with xmelab. In xrun 1-step flow, this could be fixed by using: -xmelab_args "-update".  (Default severity: 'E')

    See more info at: https://support.cadence.com/apex/Coveo_CommunitySearch#ph=Xcelium&t=PlatformProductPage&oMenu=Search&cadproduct=%22Xcelium%22&q=DLCSMD 

    If you don't care about the error, you can try using '-xmwarn DLCSMD' to try to decrease the severity from error to warning.

    Tim

Reply

  • Here's the help message from 'xmhelp xmvlog DLCSMD':

    > xmhelp xmvlog DLCSMD

    xmhelp(64): 25.04-a072: (c) Copyright 1995-2025 Cadence Design Systems, Inc.

    xmvlog/DLCSMD =

    The contents of the specified intermediate file failed a checksum test. Checksums are generated and stored in the header of a dependent intermediate file during a particular operation, as an e.g. xmvhdl. Subsequent reads of the intermediate file (as an e.g. xmelab) will generate the checksum and will verify that the data read (through xmelab) matches the data used earlier (through xmvhdl) by comparing these checksums. 

    The checksum of an intermediate file between two read operations could be different due to the following reasons.

    1) File(text) contents are different between two read operations. 

    This could be due to the fact that two design units with different contents but with the same name have been compiled in the same library. This will result in overwriting of one design unit by another and NC-Tool will generate this error on any further operation on the design unit. (please go through LRM section 11.1 for more details)

    2) Intermediate file has been recompiled but with different arguments between two read operations. 

    3) Corrupt Intermediate file.

    The probable solution to avoid the checksum mismatch is to use, "-update" with xmelab. In xrun 1-step flow, this could be fixed by using: -xmelab_args "-update".  (Default severity: 'E')

    See more info at: https://support.cadence.com/apex/Coveo_CommunitySearch#ph=Xcelium&t=PlatformProductPage&oMenu=Search&cadproduct=%22Xcelium%22&q=DLCSMD 

    If you don't care about the error, you can try using '-xmwarn DLCSMD' to try to decrease the severity from error to warning.

    Tim

Children
  • in reply to tpylant

     

    Both -xmelab_args "-update" and -xmwarn DLCSMD didn't help. I have looked also cadence support materials but they didn't help too. I am using xrun version 24.03-s001 and you can see build logs attached.

    First logs are without these flags, logs numbered with 1's for -xmelab_args "-update" flag, logs numbered with 2's for -xmwarn DLCSMD flag, there is no change in terms of errors.

    xrun_build.logxrun_build1.logxrun_build2.log

    Fullscreen xrun_build_command.log Download 
    #e1(03Jun2025:02:44:37): source /home/shc/projects/cva-soc/verification/sim/sim_build/xrun_snapshot/env.d/env.history.03Jun2025_02_44_37
s1(03Jun2025:02:44:37):  xrun -logfile xrun_build.log -elaborate -xmlibdirname /home/shc/projects/cva-soc/verification/sim/sim_build/xrun_snapshot -licqueue -clean -quiet -plinowarn -access +rwc -loadvpi /home/shc/projects/air-soc-boot/venv/lib/python3.12/site-packages/cocotb/libs/libcocotbvpi_ius.so:vlog_startup_routines_bootstrap -NEW_VHPI_PROPAGATE_DELAY -work top -newperf -plusperf -top glbl -namemap_mixgen -verbose -access +rwc -timescale 1ns/1ps -ALLOWREDEFINITION -relax -sv -v93 +incdir+"../../../vivado/cva_soc_zc706/cva_soc_zc706.gen/sources_1/ip/clk_wiz_0" -define COCOTB_SIM -incdir /home/shc/projects/cva-soc/rtl -incdir /home/shc/projects/cva-soc/rtl/sim -incdir /home/shc/projects/cva-soc/rtl/sim -incdir /home/shc/projects/cva-soc/cva6/core/include -incdir /home/shc/projects/cva-soc/cva6/core/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include/axi -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include/axi -incdir /home/shc/projects/cva-soc/cva6/common/local/util -incdir /home/shc/projects/cva-soc/cva6/common/local/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include/register_interface -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include/register_interface -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/obi/include/obi -incdir /home/shc/projects/cva-soc/obi/include/obi -incdir /home/shc/projects/cva-soc/cva6/corev_apu -incdir /home/shc/projects/cva-soc/cva6/core -incdir /home/shc/projects/cva-soc/cva6/core/frontend -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/target -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/target/cva6 -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/lint -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/scan_patterns -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/perl5 -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/perl5/Text -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/gtkwave -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sequence_lib -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/generic_cache -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/generic_cache/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/mem_model -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/mem_model/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/source -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/source/images -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/source/images/exported -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/supplement -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/release -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/source -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/source/images -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/source/_static -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/actions -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/actions/run_sequence -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/scripts -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/core/include -incdir /home/shc/projects/cva-soc/cva6/core/pmp -incdir /home/shc/projects/cva-soc/cva6/core/pmp/src -incdir /home/shc/projects/cva-soc/cva6/core/pmp/include -incdir /home/shc/projects/cva-soc/cva6/core/pmp/tb -incdir /home/shc/projects/cva-soc/cva6/core/cvxif_example -incdir /home/shc/projects/cva-soc/cva6/core/cvxif_example/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/lint -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/.github -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/ecc -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/waves -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/ci -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/document -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/examples -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/src -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/test -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/test/cmake -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/docs -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/docs/fig -incdir /home/shc/projects/cva-soc/cva6/core/cva6_mmu -incdir /home/shc/projects/cva-soc/cva6/vendor -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/examples -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/riscv_config -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/riscv_config/schemas -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/.git_hooks -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs/source -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs/source/_templates -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs/source/_static -incdir /home/shc/projects/cva-soc/cva6/vendor/patches -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/riscv -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/riscv/riscv-config -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/pulp-platform -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/pulp-platform/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include/axi -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/fpga -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc/deps -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/common -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/common/scripts -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/BramDwc -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/common -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/common/modules -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/common/include -incdir /home/shc/projects/cva-soc/cva6/common -incdir /home/shc/projects/cva-soc/cva6/common/local -incdir /home/shc/projects/cva-soc/cva6/common/local/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/scripts -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/constraints -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/ariane-ethernet -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi2apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi2apb/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_timer -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_node -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_node/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi_slice -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi_slice/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart/src/vhdl_orig -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/bootrom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/bootrom/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi_dw_adapter -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/scripts -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/test -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/.github -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/hal -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/test -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen/topgen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen/topgen/templates -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen/reggen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_protocol_checker -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_ila -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_ila/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if -incdir /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/prog -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/remote_bitbang -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/unused -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/debug_rom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/doc -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/ci -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/test -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera/constraints -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera/ip -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wb_dcache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wb_dcache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_serdiv -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_serdiv/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_dcache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_dcache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_cva6_icache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_cva6_icache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/dpi -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/wave -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_axi_dcache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_axi_dcache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/bootrom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic -incdir /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/doc -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom/baremetal -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom/linux -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom/linux/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/clint -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/lint -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include/register_interface -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/patches -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/patches/lowrisc_opentitan -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util/topgen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util/topgen/templates -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util/reggen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/docs -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/.github -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/util -incdir /home/shc/projects/cva-soc/cva6/verif/tb/core/tb_components -incdir /home/shc/projects/cva-soc/axi -incdir /home/shc/projects/cva-soc/axi/scripts -incdir /home/shc/projects/cva-soc/axi/src -incdir /home/shc/projects/cva-soc/axi/.gitlab-ci.d -incdir /home/shc/projects/cva-soc/axi/include -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/axi/.ci -incdir /home/shc/projects/cva-soc/axi/doc -incdir /home/shc/projects/cva-soc/axi/doc/svg -incdir /home/shc/projects/cva-soc/axi/.github -incdir /home/shc/projects/cva-soc/axi/.github/workflows -incdir /home/shc/projects/cva-soc/axi/test -incdir /home/shc/projects/cva-soc/obi -incdir /home/shc/projects/cva-soc/obi/src -incdir /home/shc/projects/cva-soc/obi/src/test -incdir /home/shc/projects/cva-soc/obi/include -incdir /home/shc/projects/cva-soc/obi/include/obi -incdir /home/shc/projects/cva-soc/obi/.github -incdir /home/shc/projects/cva-soc/obi/.github/workflows -incdir /home/shc/projects/cva-soc/safety_island/future/axi_obi -incdir /home/shc/projects/cva-soc/safety_island/future/axi_obi/src -incdir /home/shc/projects/cva-soc/rtl/sim -top air_soc /tools/Xilinx/Vivado/2022.2/data/vhdl/src/unisims/unisim_VCOMP.vhd /tools/Xilinx/Vivado/2022.2/data/vhdl/src/unisims/unisim_VPKG.vhd /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/obi/src/obi_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/config_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_soc_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_id_queue.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/top_pkg.sv /home/shc/projects/cva-soc/rtl/src/config/custom_config.sv /home/shc/projects/cva-soc/cva6/core/include/riscv_pkg.sv /home/shc/projects/cva-soc/rtl/src/config/custom_config.sv /home/shc/projects/cva-soc/cva6/core/include/ariane_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/build_config_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/riscv_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/config_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_axi_pkg.sv /home/shc/projects/cva-soc/axi/src/axi_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_axi_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv /home/shc/projects/cva-soc/cva6/core/include/ariane_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/wt_cache_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/std_cache_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/instr_tracer_pkg.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/ecc_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cb_filter_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/ecc_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cb_filter_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_soc_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_axi_soc_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/dm_tb_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_verif_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/top_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/tlul_pkg.sv /home/shc/projects/cva-soc/obi/src/obi_pkg.sv /home/shc/projects/cva-soc/obi/src/test/atop_golden_mem_pkg.sv /home/shc/projects/cva-soc/rtl/sim/ddr3.v /home/shc/projects/cva-soc/rtl/sim/s25fl128s.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_axi_retime.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_axi.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_dfi_seq.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_core.v /home/shc/projects/cva-soc/rtl/src/common_cells/fifo_v3.sv /home/shc/projects/cva-soc/rtl/src/common_cells/mem_to_banks_detailed.sv /home/shc/projects/cva-soc/rtl/src/common_cells/stream_fifo.sv /home/shc/projects/cva-soc/rtl/src/soc/air_soc.sv /home/shc/projects/cva-soc/rtl/src/config/custom_config.sv /home/shc/projects/cva-soc/rtl/src/memory/tc_sram_wrapper_cache_techno.sv /home/shc/projects/cva-soc/rtl/src/memory/cache.sv /home/shc/projects/cva-soc/rtl/src/memory/ram_axi.sv /home/shc/projects/cva-soc/rtl/src/memory/ram64.sv /home/shc/projects/cva-soc/rtl/src/memory/axi_synth_mem.sv /home/shc/projects/cva-soc/rtl/src/memory/simpleuart.sv /home/shc/projects/cva-soc/rtl/src/memory/tc_sram.sv /home/shc/projects/cva-soc/rtl/src/memory/bootrom.sv /home/shc/projects/cva-soc/rtl/src/memory/ram.sv /home/shc/projects/cva-soc/rtl/src/memory/ram_obi.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_handshake_fsm.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_demux.sv /home/shc/projects/cva-soc/rtl/src/databus/ram32_obi_adapter.sv /home/shc/projects/cva-soc/rtl/src/databus/obi2wishbone.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_sram_shim_modified.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_demux_mem.sv /home/shc/projects/cva-soc/rtl/src/databus/axi_to_obi_adapter.sv /home/shc/projects/cva-soc/rtl/src/databus/axi_to_dual_obi_adapter.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/dram_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/dram_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_dfi_phy.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/dram_controller_axi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer_controller_axi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/qspi/qspi_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/qspi/qspi_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_tx.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_rx.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_controller_axi.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/test/axi_riscv_atomics_synth.v /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/test/axi_riscv_lrsc_synth.v /home/shc/projects/cva-soc/cva6/core/decoder.sv /home/shc/projects/cva-soc/cva6/core/cvxif_fu.sv /home/shc/projects/cva-soc/cva6/core/cva6_rvfi_probes.sv /home/shc/projects/cva-soc/cva6/core/id_stage.sv /home/shc/projects/cva-soc/cva6/core/ariane_regfile_ff.sv /home/shc/projects/cva-soc/cva6/core/scoreboard.sv /home/shc/projects/cva-soc/cva6/core/mult.sv /home/shc/projects/cva-soc/cva6/core/serdiv.sv /home/shc/projects/cva-soc/cva6/core/cvxif_issue_register_commit_if_driver.sv /home/shc/projects/cva-soc/cva6/core/csr_regfile.sv /home/shc/projects/cva-soc/cva6/core/multiplier.sv /home/shc/projects/cva-soc/cva6/core/controller.sv /home/shc/projects/cva-soc/cva6/core/amo_buffer.sv /home/shc/projects/cva-soc/cva6/core/load_store_unit.sv /home/shc/projects/cva-soc/cva6/core/lsu_bypass.sv /home/shc/projects/cva-soc/cva6/core/axi_shim.sv /home/shc/projects/cva-soc/cva6/core/compressed_decoder.sv /home/shc/projects/cva-soc/cva6/core/instr_realign.sv /home/shc/projects/cva-soc/cva6/core/issue_read_operands.sv /home/shc/projects/cva-soc/cva6/core/cva6_accel_first_pass_decoder_stub.sv /home/shc/projects/cva-soc/cva6/core/load_unit.sv /home/shc/projects/cva-soc/cva6/core/csr_buffer.sv /home/shc/projects/cva-soc/cva6/core/cvxif_compressed_if_driver.sv /home/shc/projects/cva-soc/cva6/core/cva6_rvfi.sv /home/shc/projects/cva-soc/cva6/core/commit_stage.sv /home/shc/projects/cva-soc/cva6/core/cva6_fifo_v3.sv /home/shc/projects/cva-soc/cva6/core/store_unit.sv /home/shc/projects/cva-soc/cva6/core/acc_dispatcher.sv /home/shc/projects/cva-soc/cva6/core/ex_stage.sv /home/shc/projects/cva-soc/cva6/core/fpu_wrap.sv /home/shc/projects/cva-soc/cva6/core/issue_stage.sv /home/shc/projects/cva-soc/cva6/core/zcmt_decoder.sv /home/shc/projects/cva-soc/cva6/core/cva6.sv /home/shc/projects/cva-soc/cva6/core/macro_decoder.sv /home/shc/projects/cva-soc/cva6/core/perf_counters.sv /home/shc/projects/cva-soc/cva6/core/alu.sv /home/shc/projects/cva-soc/cva6/core/ariane_regfile.sv /home/shc/projects/cva-soc/cva6/core/branch_unit.sv /home/shc/projects/cva-soc/cva6/core/store_buffer.sv /home/shc/projects/cva-soc/cva6/core/frontend/btb.sv /home/shc/projects/cva-soc/cva6/core/frontend/instr_scan.sv /home/shc/projects/cva-soc/cva6/core/frontend/frontend.sv /home/shc/projects/cva-soc/cva6/core/frontend/bht.sv /home/shc/projects/cva-soc/cva6/core/frontend/instr_queue.sv /home/shc/projects/cva-soc/cva6/core/frontend/ras.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_axi_adapter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_if_adapter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_cache_subsystem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/axi_adapter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_ctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_mem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_icache_axi_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/miss_handler.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/amo_alu.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_icache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/std_nbdcache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cache_ctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_missunit.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/std_cache_subsystem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/tag_cmp.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_subsystem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_wbuffer.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_ptw.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_tlb.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_mmu.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_shared_tlb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/lint/hpdcache_lint.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_l15_resp_demux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_l15_req_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_resize.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fxarb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_lfsr.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg_initialized.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_demux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_mux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_upsize.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sync_buffer.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_downsize.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wmask_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_rrarb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv /home/shc/projects/cva-soc/cva6/core/pmp/src/pmp.sv /home/shc/projects/cva-soc/cva6/core/pmp/src/pmp_data_if.sv /home/shc/projects/cva-soc/cva6/core/pmp/src/pmp_entry.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_cast_multi.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_fma_multi.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_noncomp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_fma.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_opgroup_block.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_rounding.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_top.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_divsqrt_multi.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_classifier.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lfsr_8bit.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_xbar.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_filter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/delta_counter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/popcount.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_to_mem.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lfsr.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_detect.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/rstgen.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/gray_to_binary.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/fifo_v3.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lfsr_16bit.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_propagator_rx.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/ecc_encode.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/serial_deglitch.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_intf.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/id_queue.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/ecc_decode.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_arbiter_flushable.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/rstgen_bypass.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/plru_tree.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_demux.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/addr_decode.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_join.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cdc_fifo_2phase.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/sub_per_hash.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/unread.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_omega_net.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/binary_to_gray.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_propagator_tx.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/clk_div.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_fork_dynamic.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/sync.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_mux.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/isochronous_spill_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/sync_wedge.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cdc_2phase.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_fork.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/counter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/exp_backoff.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_propagator.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cb_filter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_delay.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lzc.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/spill_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/onehot_to_bin.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cdc_fifo_gray.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/mv_filter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/shift_reg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/max_counter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/rr_arb_tree.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_fifo.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/fall_through_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/stream_arbiter_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/id_queue_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/cdc_2phase_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/synth_bench.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/ecc_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/stream_test.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal/counter_properties.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal/fifo_v3_properties.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal/fall_through_register_properties.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_xbar.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/popcount.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_to_mem.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_detect.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/rstgen.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/gray_to_binary.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lfsr_16bit.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_propagator_rx.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/ecc_encode.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/serial_deglitch.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/isochronous_4phase_handshake.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_intf.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/id_queue.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/ecc_decode.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/plru_tree.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_demux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/addr_decode.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_join.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cdc_fifo_2phase.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/sub_per_hash.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/unread.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_omega_net.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/binary_to_gray.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_propagator_tx.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/clk_div.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_fork_dynamic.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/sync.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_mux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/isochronous_spill_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/sync_wedge.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_fork.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/counter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/exp_backoff.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_propagator.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cb_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_delay.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lzc.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/onehot_to_bin.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cdc_fifo_gray.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/mv_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/shift_reg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cc_onehot.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/max_counter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_fifo.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/fall_through_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cdc_dst.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_sim_mem.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_mux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_regs.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_serializer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_iw_converter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_demux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_to_apb.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_mux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_mailbox.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_burst_splitter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_dw_upsizer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_multicut.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_delayer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_dw_converter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cdc_src.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cdc.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_err_slv.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_demux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_to_axi.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cut.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_id_remap.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_join.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_xbar.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_modify_address.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_to_axi_lite.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_id_prepend.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_isolate.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_test.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_intf.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_dw_downsizer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_join.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/tc_pwr.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv /home/shc/projects/cva-soc/cva6/common/local/util/hpdcache_sram_wbyteenable_1rw.sv /home/shc/projects/cva-soc/cva6/common/local/util/find_first_one.sv /home/shc/projects/cva-soc/cva6/common/local/util/hpdcache_sram_1rw.sv /home/shc/projects/cva-soc/cva6/common/local/util/tc_sram_wrapper.sv /home/shc/projects/cva-soc/cva6/common/local/util/sram_cache.sv /home/shc/projects/cva-soc/cva6/common/local/util/instr_tracer.sv /home/shc/projects/cva-soc/cva6/common/local/util/sram.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/ariane.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_peripherals.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_testharness.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/rvfi_tracer.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/axi_intf.sv /home/shc/projects/cva-soc/cva6/corev_apu/bootrom/bootrom.sv /home/shc/projects/cva-soc/cva6/corev_apu/clint/axi_lite_interface.sv /home/shc/projects/cva-soc/cva6/corev_apu/clint/clint.sv /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if/src/axi2mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_obi_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dmi_cdc.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_sba.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/dp_ram.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/mm_ram.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/boot_rom.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom_one_scratch.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva/dm_sba_sva.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva/dm_top_sva.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva/dm_csrs_sva.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_res_tbl.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/uart.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/dp_ram.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/mock_uart.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/core_mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_synch_holdable_driver.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_synch_driver.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/sim_timeout.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_stream_mst.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/clk_rst_gen.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_stream_slv.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_id_queue.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_target.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/prim_subreg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/plic_regmap.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_gateway.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/prim_subreg_ext.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_reg_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/plic_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_test.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_mux.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_demux.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_intf.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/axi_lite_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_uniform.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_to_mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/apb_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/periph_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/axi_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_cdc.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_shadow.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_arb.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_ext.sv /home/shc/projects/cva-soc/cva6/verif/tb/core/tb_components/axi_master_connect.sv /home/shc/projects/cva-soc/axi/src/axi_atop_filter.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem_interleaved.sv /home/shc/projects/cva-soc/axi/src/axi_cdc_dst.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem_split.sv /home/shc/projects/cva-soc/axi/src/axi_lite_from_mem.sv /home/shc/projects/cva-soc/axi/src/axi_sim_mem.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem.sv /home/shc/projects/cva-soc/axi/src/axi_lite_mux.sv /home/shc/projects/cva-soc/axi/src/axi_dumper.sv /home/shc/projects/cva-soc/axi/src/axi_chan_compare.sv /home/shc/projects/cva-soc/axi/src/axi_lite_regs.sv /home/shc/projects/cva-soc/axi/src/axi_serializer.sv /home/shc/projects/cva-soc/axi/src/axi_interleaved_xbar.sv /home/shc/projects/cva-soc/axi/src/axi_iw_converter.sv /home/shc/projects/cva-soc/axi/src/axi_demux.sv /home/shc/projects/cva-soc/axi/src/axi_lite_to_apb.sv /home/shc/projects/cva-soc/axi/src/axi_mux.sv /home/shc/projects/cva-soc/axi/src/axi_to_detailed_mem.sv /home/shc/projects/cva-soc/axi/src/axi_from_mem.sv /home/shc/projects/cva-soc/axi/src/axi_lite_mailbox.sv /home/shc/projects/cva-soc/axi/src/axi_burst_splitter.sv /home/shc/projects/cva-soc/axi/src/axi_dw_upsizer.sv /home/shc/projects/cva-soc/axi/src/axi_multicut.sv /home/shc/projects/cva-soc/axi/src/axi_delayer.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem_banked.sv /home/shc/projects/cva-soc/axi/src/axi_rw_split.sv /home/shc/projects/cva-soc/axi/src/axi_xbar_unmuxed.sv /home/shc/projects/cva-soc/axi/src/axi_dw_converter.sv /home/shc/projects/cva-soc/axi/src/axi_rw_join.sv /home/shc/projects/cva-soc/axi/src/axi_cdc_src.sv /home/shc/projects/cva-soc/axi/src/axi_cdc.sv /home/shc/projects/cva-soc/axi/src/axi_err_slv.sv /home/shc/projects/cva-soc/axi/src/axi_lite_demux.sv /home/shc/projects/cva-soc/axi/src/axi_lite_to_axi.sv /home/shc/projects/cva-soc/axi/src/axi_throttle.sv /home/shc/projects/cva-soc/axi/src/axi_cut.sv /home/shc/projects/cva-soc/axi/src/axi_id_remap.sv /home/shc/projects/cva-soc/axi/src/axi_bus_compare.sv /home/shc/projects/cva-soc/axi/src/axi_lite_join.sv /home/shc/projects/cva-soc/axi/src/axi_lite_xbar.sv /home/shc/projects/cva-soc/axi/src/axi_lite_dw_converter.sv /home/shc/projects/cva-soc/axi/src/axi_slave_compare.sv /home/shc/projects/cva-soc/axi/src/axi_modify_address.sv /home/shc/projects/cva-soc/axi/src/axi_lfsr.sv /home/shc/projects/cva-soc/axi/src/axi_to_axi_lite.sv /home/shc/projects/cva-soc/axi/src/axi_id_prepend.sv /home/shc/projects/cva-soc/axi/src/axi_isolate.sv /home/shc/projects/cva-soc/axi/src/axi_fifo.sv /home/shc/projects/cva-soc/axi/src/axi_test.sv /home/shc/projects/cva-soc/axi/src/axi_xbar.sv /home/shc/projects/cva-soc/axi/src/axi_intf.sv /home/shc/projects/cva-soc/axi/src/axi_dw_downsizer.sv /home/shc/projects/cva-soc/axi/src/axi_join.sv /home/shc/projects/cva-soc/axi/src/axi_demux_simple.sv /home/shc/projects/cva-soc/axi/src/axi_xp.sv /home/shc/projects/cva-soc/axi/test/axi_synth_bench.sv /home/shc/projects/cva-soc/obi/src/obi_sram_shim.sv /home/shc/projects/cva-soc/obi/src/obi_mux.sv /home/shc/projects/cva-soc/obi/src/obi_intf.sv /home/shc/projects/cva-soc/obi/src/obi_demux.sv /home/shc/projects/cva-soc/obi/src/obi_cut.sv /home/shc/projects/cva-soc/obi/src/obi_rready_converter.sv /home/shc/projects/cva-soc/obi/src/obi_xbar.sv /home/shc/projects/cva-soc/obi/src/obi_err_sbr.sv /home/shc/projects/cva-soc/obi/src/test/obi_test.sv /home/shc/projects/cva-soc/obi/src/test/obi_sim_mem.sv /home/shc/projects/cva-soc/obi/src/test/obi_asserter.sv /home/shc/projects/cva-soc/safety_island/future/axi_obi/src/axi_to_obi.sv /home/shc/projects/cva-soc/safety_island/future/axi_obi/src/obi_to_axi.sv /home/shc/projects/cva-soc/safety_island/future/axi_obi/src/axi_to_detailed_mem_user.sv /home/shc/projects/cva-soc/vivado/cva_soc_zc706/cva_soc_zc706.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/glbl.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/OBUFDS.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IOBUFDS.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/OSERDESE2.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/ISERDESE2.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IOBUF.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IDELAYE2.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IDELAYCTRL.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/BUFG.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IBUFDS.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/MMCME2_ADV.v
    Fullscreen xrun_build_command1.log Download 
    #e1(03Jun2025:02:45:54): source /home/shc/projects/cva-soc/verification/sim/sim_build/xrun_snapshot/env.d/env.history.03Jun2025_02_45_54
s1(03Jun2025:02:45:54):  xrun -logfile xrun_build.log -elaborate -xmlibdirname /home/shc/projects/cva-soc/verification/sim/sim_build/xrun_snapshot -licqueue -clean -quiet -plinowarn -access +rwc -loadvpi /home/shc/projects/air-soc-boot/venv/lib/python3.12/site-packages/cocotb/libs/libcocotbvpi_ius.so:vlog_startup_routines_bootstrap -NEW_VHPI_PROPAGATE_DELAY -work top -xmelab_args "-update" -newperf -plusperf -top glbl -namemap_mixgen -verbose -access +rwc -timescale 1ns/1ps -ALLOWREDEFINITION -relax -sv -v93 +incdir+"../../../vivado/cva_soc_zc706/cva_soc_zc706.gen/sources_1/ip/clk_wiz_0" -define COCOTB_SIM -incdir /home/shc/projects/cva-soc/rtl -incdir /home/shc/projects/cva-soc/rtl/sim -incdir /home/shc/projects/cva-soc/rtl/sim -incdir /home/shc/projects/cva-soc/cva6/core/include -incdir /home/shc/projects/cva-soc/cva6/core/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include/axi -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include/axi -incdir /home/shc/projects/cva-soc/cva6/common/local/util -incdir /home/shc/projects/cva-soc/cva6/common/local/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include/register_interface -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include/register_interface -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/obi/include/obi -incdir /home/shc/projects/cva-soc/obi/include/obi -incdir /home/shc/projects/cva-soc/cva6/corev_apu -incdir /home/shc/projects/cva-soc/cva6/core -incdir /home/shc/projects/cva-soc/cva6/core/frontend -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/target -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/target/cva6 -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/lint -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/scan_patterns -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/perl5 -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/perl5/Text -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/gtkwave -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sequence_lib -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/generic_cache -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/generic_cache/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/mem_model -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/mem_model/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/source -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/source/images -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/source/images/exported -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/supplement -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/release -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/source -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/source/images -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/source/_static -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/actions -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/actions/run_sequence -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/scripts -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/core/include -incdir /home/shc/projects/cva-soc/cva6/core/pmp -incdir /home/shc/projects/cva-soc/cva6/core/pmp/src -incdir /home/shc/projects/cva-soc/cva6/core/pmp/include -incdir /home/shc/projects/cva-soc/cva6/core/pmp/tb -incdir /home/shc/projects/cva-soc/cva6/core/cvxif_example -incdir /home/shc/projects/cva-soc/cva6/core/cvxif_example/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/lint -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/.github -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/ecc -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/waves -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/ci -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/document -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/examples -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/src -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/test -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/test/cmake -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/docs -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/docs/fig -incdir /home/shc/projects/cva-soc/cva6/core/cva6_mmu -incdir /home/shc/projects/cva-soc/cva6/vendor -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/examples -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/riscv_config -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/riscv_config/schemas -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/.git_hooks -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs/source -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs/source/_templates -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs/source/_static -incdir /home/shc/projects/cva-soc/cva6/vendor/patches -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/riscv -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/riscv/riscv-config -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/pulp-platform -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/pulp-platform/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include/axi -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/fpga -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc/deps -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/common -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/common/scripts -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/BramDwc -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/common -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/common/modules -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/common/include -incdir /home/shc/projects/cva-soc/cva6/common -incdir /home/shc/projects/cva-soc/cva6/common/local -incdir /home/shc/projects/cva-soc/cva6/common/local/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/scripts -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/constraints -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/ariane-ethernet -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi2apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi2apb/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_timer -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_node -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_node/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi_slice -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi_slice/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart/src/vhdl_orig -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/bootrom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/bootrom/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi_dw_adapter -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/scripts -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/test -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/.github -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/hal -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/test -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen/topgen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen/topgen/templates -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen/reggen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_protocol_checker -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_ila -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_ila/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if -incdir /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/prog -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/remote_bitbang -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/unused -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/debug_rom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/doc -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/ci -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/test -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera/constraints -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera/ip -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wb_dcache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wb_dcache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_serdiv -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_serdiv/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_dcache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_dcache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_cva6_icache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_cva6_icache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/dpi -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/wave -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_axi_dcache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_axi_dcache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/bootrom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic -incdir /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/doc -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom/baremetal -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom/linux -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom/linux/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/clint -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/lint -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include/register_interface -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/patches -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/patches/lowrisc_opentitan -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util/topgen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util/topgen/templates -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util/reggen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/docs -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/.github -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/util -incdir /home/shc/projects/cva-soc/cva6/verif/tb/core/tb_components -incdir /home/shc/projects/cva-soc/axi -incdir /home/shc/projects/cva-soc/axi/scripts -incdir /home/shc/projects/cva-soc/axi/src -incdir /home/shc/projects/cva-soc/axi/.gitlab-ci.d -incdir /home/shc/projects/cva-soc/axi/include -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/axi/.ci -incdir /home/shc/projects/cva-soc/axi/doc -incdir /home/shc/projects/cva-soc/axi/doc/svg -incdir /home/shc/projects/cva-soc/axi/.github -incdir /home/shc/projects/cva-soc/axi/.github/workflows -incdir /home/shc/projects/cva-soc/axi/test -incdir /home/shc/projects/cva-soc/obi -incdir /home/shc/projects/cva-soc/obi/src -incdir /home/shc/projects/cva-soc/obi/src/test -incdir /home/shc/projects/cva-soc/obi/include -incdir /home/shc/projects/cva-soc/obi/include/obi -incdir /home/shc/projects/cva-soc/obi/.github -incdir /home/shc/projects/cva-soc/obi/.github/workflows -incdir /home/shc/projects/cva-soc/safety_island/future/axi_obi -incdir /home/shc/projects/cva-soc/safety_island/future/axi_obi/src -incdir /home/shc/projects/cva-soc/rtl/sim -top air_soc /tools/Xilinx/Vivado/2022.2/data/vhdl/src/unisims/unisim_VCOMP.vhd /tools/Xilinx/Vivado/2022.2/data/vhdl/src/unisims/unisim_VPKG.vhd /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/obi/src/obi_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/config_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_soc_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_id_queue.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/top_pkg.sv /home/shc/projects/cva-soc/rtl/src/config/custom_config.sv /home/shc/projects/cva-soc/cva6/core/include/riscv_pkg.sv /home/shc/projects/cva-soc/rtl/src/config/custom_config.sv /home/shc/projects/cva-soc/cva6/core/include/ariane_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/build_config_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/riscv_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/config_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_axi_pkg.sv /home/shc/projects/cva-soc/axi/src/axi_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_axi_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv /home/shc/projects/cva-soc/cva6/core/include/ariane_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/wt_cache_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/std_cache_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/instr_tracer_pkg.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/ecc_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cb_filter_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/ecc_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cb_filter_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_soc_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_axi_soc_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/dm_tb_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_verif_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/top_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/tlul_pkg.sv /home/shc/projects/cva-soc/obi/src/obi_pkg.sv /home/shc/projects/cva-soc/obi/src/test/atop_golden_mem_pkg.sv /home/shc/projects/cva-soc/rtl/sim/ddr3.v /home/shc/projects/cva-soc/rtl/sim/s25fl128s.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_axi_retime.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_axi.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_dfi_seq.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_core.v /home/shc/projects/cva-soc/rtl/src/common_cells/fifo_v3.sv /home/shc/projects/cva-soc/rtl/src/common_cells/mem_to_banks_detailed.sv /home/shc/projects/cva-soc/rtl/src/common_cells/stream_fifo.sv /home/shc/projects/cva-soc/rtl/src/soc/air_soc.sv /home/shc/projects/cva-soc/rtl/src/config/custom_config.sv /home/shc/projects/cva-soc/rtl/src/memory/tc_sram_wrapper_cache_techno.sv /home/shc/projects/cva-soc/rtl/src/memory/cache.sv /home/shc/projects/cva-soc/rtl/src/memory/ram_axi.sv /home/shc/projects/cva-soc/rtl/src/memory/ram64.sv /home/shc/projects/cva-soc/rtl/src/memory/axi_synth_mem.sv /home/shc/projects/cva-soc/rtl/src/memory/simpleuart.sv /home/shc/projects/cva-soc/rtl/src/memory/tc_sram.sv /home/shc/projects/cva-soc/rtl/src/memory/bootrom.sv /home/shc/projects/cva-soc/rtl/src/memory/ram.sv /home/shc/projects/cva-soc/rtl/src/memory/ram_obi.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_handshake_fsm.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_demux.sv /home/shc/projects/cva-soc/rtl/src/databus/ram32_obi_adapter.sv /home/shc/projects/cva-soc/rtl/src/databus/obi2wishbone.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_sram_shim_modified.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_demux_mem.sv /home/shc/projects/cva-soc/rtl/src/databus/axi_to_obi_adapter.sv /home/shc/projects/cva-soc/rtl/src/databus/axi_to_dual_obi_adapter.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/dram_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/dram_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_dfi_phy.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/dram_controller_axi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer_controller_axi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/qspi/qspi_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/qspi/qspi_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_tx.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_rx.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_controller_axi.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/test/axi_riscv_atomics_synth.v /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/test/axi_riscv_lrsc_synth.v /home/shc/projects/cva-soc/cva6/core/decoder.sv /home/shc/projects/cva-soc/cva6/core/cvxif_fu.sv /home/shc/projects/cva-soc/cva6/core/cva6_rvfi_probes.sv /home/shc/projects/cva-soc/cva6/core/id_stage.sv /home/shc/projects/cva-soc/cva6/core/ariane_regfile_ff.sv /home/shc/projects/cva-soc/cva6/core/scoreboard.sv /home/shc/projects/cva-soc/cva6/core/mult.sv /home/shc/projects/cva-soc/cva6/core/serdiv.sv /home/shc/projects/cva-soc/cva6/core/cvxif_issue_register_commit_if_driver.sv /home/shc/projects/cva-soc/cva6/core/csr_regfile.sv /home/shc/projects/cva-soc/cva6/core/multiplier.sv /home/shc/projects/cva-soc/cva6/core/controller.sv /home/shc/projects/cva-soc/cva6/core/amo_buffer.sv /home/shc/projects/cva-soc/cva6/core/load_store_unit.sv /home/shc/projects/cva-soc/cva6/core/lsu_bypass.sv /home/shc/projects/cva-soc/cva6/core/axi_shim.sv /home/shc/projects/cva-soc/cva6/core/compressed_decoder.sv /home/shc/projects/cva-soc/cva6/core/instr_realign.sv /home/shc/projects/cva-soc/cva6/core/issue_read_operands.sv /home/shc/projects/cva-soc/cva6/core/cva6_accel_first_pass_decoder_stub.sv /home/shc/projects/cva-soc/cva6/core/load_unit.sv /home/shc/projects/cva-soc/cva6/core/csr_buffer.sv /home/shc/projects/cva-soc/cva6/core/cvxif_compressed_if_driver.sv /home/shc/projects/cva-soc/cva6/core/cva6_rvfi.sv /home/shc/projects/cva-soc/cva6/core/commit_stage.sv /home/shc/projects/cva-soc/cva6/core/cva6_fifo_v3.sv /home/shc/projects/cva-soc/cva6/core/store_unit.sv /home/shc/projects/cva-soc/cva6/core/acc_dispatcher.sv /home/shc/projects/cva-soc/cva6/core/ex_stage.sv /home/shc/projects/cva-soc/cva6/core/fpu_wrap.sv /home/shc/projects/cva-soc/cva6/core/issue_stage.sv /home/shc/projects/cva-soc/cva6/core/zcmt_decoder.sv /home/shc/projects/cva-soc/cva6/core/cva6.sv /home/shc/projects/cva-soc/cva6/core/macro_decoder.sv /home/shc/projects/cva-soc/cva6/core/perf_counters.sv /home/shc/projects/cva-soc/cva6/core/alu.sv /home/shc/projects/cva-soc/cva6/core/ariane_regfile.sv /home/shc/projects/cva-soc/cva6/core/branch_unit.sv /home/shc/projects/cva-soc/cva6/core/store_buffer.sv /home/shc/projects/cva-soc/cva6/core/frontend/btb.sv /home/shc/projects/cva-soc/cva6/core/frontend/instr_scan.sv /home/shc/projects/cva-soc/cva6/core/frontend/frontend.sv /home/shc/projects/cva-soc/cva6/core/frontend/bht.sv /home/shc/projects/cva-soc/cva6/core/frontend/instr_queue.sv /home/shc/projects/cva-soc/cva6/core/frontend/ras.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_axi_adapter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_if_adapter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_cache_subsystem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/axi_adapter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_ctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_mem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_icache_axi_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/miss_handler.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/amo_alu.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_icache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/std_nbdcache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cache_ctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_missunit.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/std_cache_subsystem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/tag_cmp.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_subsystem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_wbuffer.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_ptw.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_tlb.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_mmu.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_shared_tlb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/lint/hpdcache_lint.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_l15_resp_demux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_l15_req_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_resize.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fxarb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_lfsr.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg_initialized.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_demux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_mux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_upsize.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sync_buffer.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_downsize.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wmask_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_rrarb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv /home/shc/projects/cva-soc/cva6/core/pmp/src/pmp.sv /home/shc/projects/cva-soc/cva6/core/pmp/src/pmp_data_if.sv /home/shc/projects/cva-soc/cva6/core/pmp/src/pmp_entry.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_cast_multi.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_fma_multi.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_noncomp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_fma.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_opgroup_block.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_rounding.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_top.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_divsqrt_multi.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_classifier.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lfsr_8bit.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_xbar.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_filter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/delta_counter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/popcount.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_to_mem.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lfsr.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_detect.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/rstgen.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/gray_to_binary.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/fifo_v3.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lfsr_16bit.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_propagator_rx.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/ecc_encode.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/serial_deglitch.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_intf.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/id_queue.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/ecc_decode.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_arbiter_flushable.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/rstgen_bypass.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/plru_tree.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_demux.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/addr_decode.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_join.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cdc_fifo_2phase.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/sub_per_hash.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/unread.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_omega_net.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/binary_to_gray.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_propagator_tx.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/clk_div.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_fork_dynamic.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/sync.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_mux.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/isochronous_spill_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/sync_wedge.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cdc_2phase.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_fork.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/counter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/exp_backoff.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_propagator.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cb_filter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_delay.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lzc.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/spill_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/onehot_to_bin.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cdc_fifo_gray.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/mv_filter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/shift_reg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/max_counter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/rr_arb_tree.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_fifo.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/fall_through_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/stream_arbiter_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/id_queue_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/cdc_2phase_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/synth_bench.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/ecc_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/stream_test.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal/counter_properties.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal/fifo_v3_properties.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal/fall_through_register_properties.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_xbar.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/popcount.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_to_mem.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_detect.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/rstgen.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/gray_to_binary.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lfsr_16bit.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_propagator_rx.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/ecc_encode.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/serial_deglitch.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/isochronous_4phase_handshake.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_intf.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/id_queue.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/ecc_decode.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/plru_tree.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_demux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/addr_decode.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_join.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cdc_fifo_2phase.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/sub_per_hash.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/unread.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_omega_net.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/binary_to_gray.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_propagator_tx.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/clk_div.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_fork_dynamic.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/sync.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_mux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/isochronous_spill_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/sync_wedge.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_fork.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/counter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/exp_backoff.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_propagator.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cb_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_delay.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lzc.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/onehot_to_bin.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cdc_fifo_gray.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/mv_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/shift_reg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cc_onehot.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/max_counter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_fifo.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/fall_through_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cdc_dst.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_sim_mem.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_mux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_regs.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_serializer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_iw_converter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_demux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_to_apb.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_mux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_mailbox.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_burst_splitter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_dw_upsizer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_multicut.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_delayer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_dw_converter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cdc_src.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cdc.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_err_slv.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_demux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_to_axi.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cut.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_id_remap.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_join.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_xbar.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_modify_address.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_to_axi_lite.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_id_prepend.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_isolate.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_test.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_intf.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_dw_downsizer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_join.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/tc_pwr.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv /home/shc/projects/cva-soc/cva6/common/local/util/hpdcache_sram_wbyteenable_1rw.sv /home/shc/projects/cva-soc/cva6/common/local/util/find_first_one.sv /home/shc/projects/cva-soc/cva6/common/local/util/hpdcache_sram_1rw.sv /home/shc/projects/cva-soc/cva6/common/local/util/tc_sram_wrapper.sv /home/shc/projects/cva-soc/cva6/common/local/util/sram_cache.sv /home/shc/projects/cva-soc/cva6/common/local/util/instr_tracer.sv /home/shc/projects/cva-soc/cva6/common/local/util/sram.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/ariane.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_peripherals.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_testharness.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/rvfi_tracer.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/axi_intf.sv /home/shc/projects/cva-soc/cva6/corev_apu/bootrom/bootrom.sv /home/shc/projects/cva-soc/cva6/corev_apu/clint/axi_lite_interface.sv /home/shc/projects/cva-soc/cva6/corev_apu/clint/clint.sv /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if/src/axi2mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_obi_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dmi_cdc.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_sba.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/dp_ram.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/mm_ram.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/boot_rom.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom_one_scratch.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva/dm_sba_sva.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva/dm_top_sva.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva/dm_csrs_sva.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_res_tbl.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/uart.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/dp_ram.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/mock_uart.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/core_mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_synch_holdable_driver.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_synch_driver.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/sim_timeout.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_stream_mst.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/clk_rst_gen.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_stream_slv.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_id_queue.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_target.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/prim_subreg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/plic_regmap.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_gateway.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/prim_subreg_ext.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_reg_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/plic_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_test.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_mux.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_demux.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_intf.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/axi_lite_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_uniform.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_to_mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/apb_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/periph_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/axi_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_cdc.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_shadow.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_arb.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_ext.sv /home/shc/projects/cva-soc/cva6/verif/tb/core/tb_components/axi_master_connect.sv /home/shc/projects/cva-soc/axi/src/axi_atop_filter.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem_interleaved.sv /home/shc/projects/cva-soc/axi/src/axi_cdc_dst.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem_split.sv /home/shc/projects/cva-soc/axi/src/axi_lite_from_mem.sv /home/shc/projects/cva-soc/axi/src/axi_sim_mem.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem.sv /home/shc/projects/cva-soc/axi/src/axi_lite_mux.sv /home/shc/projects/cva-soc/axi/src/axi_dumper.sv /home/shc/projects/cva-soc/axi/src/axi_chan_compare.sv /home/shc/projects/cva-soc/axi/src/axi_lite_regs.sv /home/shc/projects/cva-soc/axi/src/axi_serializer.sv /home/shc/projects/cva-soc/axi/src/axi_interleaved_xbar.sv /home/shc/projects/cva-soc/axi/src/axi_iw_converter.sv /home/shc/projects/cva-soc/axi/src/axi_demux.sv /home/shc/projects/cva-soc/axi/src/axi_lite_to_apb.sv /home/shc/projects/cva-soc/axi/src/axi_mux.sv /home/shc/projects/cva-soc/axi/src/axi_to_detailed_mem.sv /home/shc/projects/cva-soc/axi/src/axi_from_mem.sv /home/shc/projects/cva-soc/axi/src/axi_lite_mailbox.sv /home/shc/projects/cva-soc/axi/src/axi_burst_splitter.sv /home/shc/projects/cva-soc/axi/src/axi_dw_upsizer.sv /home/shc/projects/cva-soc/axi/src/axi_multicut.sv /home/shc/projects/cva-soc/axi/src/axi_delayer.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem_banked.sv /home/shc/projects/cva-soc/axi/src/axi_rw_split.sv /home/shc/projects/cva-soc/axi/src/axi_xbar_unmuxed.sv /home/shc/projects/cva-soc/axi/src/axi_dw_converter.sv /home/shc/projects/cva-soc/axi/src/axi_rw_join.sv /home/shc/projects/cva-soc/axi/src/axi_cdc_src.sv /home/shc/projects/cva-soc/axi/src/axi_cdc.sv /home/shc/projects/cva-soc/axi/src/axi_err_slv.sv /home/shc/projects/cva-soc/axi/src/axi_lite_demux.sv /home/shc/projects/cva-soc/axi/src/axi_lite_to_axi.sv /home/shc/projects/cva-soc/axi/src/axi_throttle.sv /home/shc/projects/cva-soc/axi/src/axi_cut.sv /home/shc/projects/cva-soc/axi/src/axi_id_remap.sv /home/shc/projects/cva-soc/axi/src/axi_bus_compare.sv /home/shc/projects/cva-soc/axi/src/axi_lite_join.sv /home/shc/projects/cva-soc/axi/src/axi_lite_xbar.sv /home/shc/projects/cva-soc/axi/src/axi_lite_dw_converter.sv /home/shc/projects/cva-soc/axi/src/axi_slave_compare.sv /home/shc/projects/cva-soc/axi/src/axi_modify_address.sv /home/shc/projects/cva-soc/axi/src/axi_lfsr.sv /home/shc/projects/cva-soc/axi/src/axi_to_axi_lite.sv /home/shc/projects/cva-soc/axi/src/axi_id_prepend.sv /home/shc/projects/cva-soc/axi/src/axi_isolate.sv /home/shc/projects/cva-soc/axi/src/axi_fifo.sv /home/shc/projects/cva-soc/axi/src/axi_test.sv /home/shc/projects/cva-soc/axi/src/axi_xbar.sv /home/shc/projects/cva-soc/axi/src/axi_intf.sv /home/shc/projects/cva-soc/axi/src/axi_dw_downsizer.sv /home/shc/projects/cva-soc/axi/src/axi_join.sv /home/shc/projects/cva-soc/axi/src/axi_demux_simple.sv /home/shc/projects/cva-soc/axi/src/axi_xp.sv /home/shc/projects/cva-soc/axi/test/axi_synth_bench.sv /home/shc/projects/cva-soc/obi/src/obi_sram_shim.sv /home/shc/projects/cva-soc/obi/src/obi_mux.sv /home/shc/projects/cva-soc/obi/src/obi_intf.sv /home/shc/projects/cva-soc/obi/src/obi_demux.sv /home/shc/projects/cva-soc/obi/src/obi_cut.sv /home/shc/projects/cva-soc/obi/src/obi_rready_converter.sv /home/shc/projects/cva-soc/obi/src/obi_xbar.sv /home/shc/projects/cva-soc/obi/src/obi_err_sbr.sv /home/shc/projects/cva-soc/obi/src/test/obi_test.sv /home/shc/projects/cva-soc/obi/src/test/obi_sim_mem.sv /home/shc/projects/cva-soc/obi/src/test/obi_asserter.sv /home/shc/projects/cva-soc/safety_island/future/axi_obi/src/axi_to_obi.sv /home/shc/projects/cva-soc/safety_island/future/axi_obi/src/obi_to_axi.sv /home/shc/projects/cva-soc/safety_island/future/axi_obi/src/axi_to_detailed_mem_user.sv /home/shc/projects/cva-soc/vivado/cva_soc_zc706/cva_soc_zc706.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/glbl.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/OBUFDS.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IOBUFDS.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/OSERDESE2.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/ISERDESE2.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IOBUF.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IDELAYE2.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IDELAYCTRL.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/BUFG.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IBUFDS.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/MMCME2_ADV.v
    Fullscreen xrun_build_command2.log Download 
    #e1(03Jun2025:02:47:01): source /home/shc/projects/cva-soc/verification/sim/sim_build/xrun_snapshot/env.d/env.history.03Jun2025_02_47_01
s1(03Jun2025:02:47:01):  xrun -logfile xrun_build.log -elaborate -xmlibdirname /home/shc/projects/cva-soc/verification/sim/sim_build/xrun_snapshot -licqueue -clean -quiet -plinowarn -access +rwc -loadvpi /home/shc/projects/air-soc-boot/venv/lib/python3.12/site-packages/cocotb/libs/libcocotbvpi_ius.so:vlog_startup_routines_bootstrap -NEW_VHPI_PROPAGATE_DELAY -work top -xmwarn DLCSMD -newperf -plusperf -top glbl -namemap_mixgen -verbose -access +rwc -timescale 1ns/1ps -ALLOWREDEFINITION -relax -sv -v93 +incdir+"../../../vivado/cva_soc_zc706/cva_soc_zc706.gen/sources_1/ip/clk_wiz_0" -define COCOTB_SIM -incdir /home/shc/projects/cva-soc/rtl -incdir /home/shc/projects/cva-soc/rtl/sim -incdir /home/shc/projects/cva-soc/rtl/sim -incdir /home/shc/projects/cva-soc/cva6/core/include -incdir /home/shc/projects/cva-soc/cva6/core/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include/axi -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include/axi -incdir /home/shc/projects/cva-soc/cva6/common/local/util -incdir /home/shc/projects/cva-soc/cva6/common/local/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include/register_interface -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include/register_interface -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/obi/include/obi -incdir /home/shc/projects/cva-soc/obi/include/obi -incdir /home/shc/projects/cva-soc/cva6/corev_apu -incdir /home/shc/projects/cva-soc/cva6/core -incdir /home/shc/projects/cva-soc/cva6/core/frontend -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/target -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/target/cva6 -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/lint -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/scan_patterns -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/perl5 -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/perl5/Text -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/scripts/gtkwave -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sequence_lib -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/generic_cache -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/generic_cache/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/mem_model -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/modules/mem_model/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/tb/sc_verif_lib/include -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/source -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/source/images -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/source/images/exported -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/supplement -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/old/release -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/source -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/source/images -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/docs/source/_static -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/actions -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/actions/run_sequence -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/scripts -incdir /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/core/include -incdir /home/shc/projects/cva-soc/cva6/core/pmp -incdir /home/shc/projects/cva-soc/cva6/core/pmp/src -incdir /home/shc/projects/cva-soc/cva6/core/pmp/include -incdir /home/shc/projects/cva-soc/cva6/core/pmp/tb -incdir /home/shc/projects/cva-soc/cva6/core/cvxif_example -incdir /home/shc/projects/cva-soc/cva6/core/cvxif_example/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/lint -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/.github -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/ecc -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/waves -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/ci -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/document -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/examples -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/src -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/include -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/test -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/tb/flexfloat/test/cmake -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/docs -incdir /home/shc/projects/cva-soc/cva6/core/cvfpu/docs/fig -incdir /home/shc/projects/cva-soc/cva6/core/cva6_mmu -incdir /home/shc/projects/cva-soc/cva6/vendor -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/examples -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/riscv_config -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/riscv_config/schemas -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/.git_hooks -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs/source -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs/source/_templates -incdir /home/shc/projects/cva-soc/cva6/vendor/riscv/riscv-config/docs/source/_static -incdir /home/shc/projects/cva-soc/cva6/vendor/patches -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/riscv -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/riscv/riscv-config -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/pulp-platform -incdir /home/shc/projects/cva-soc/cva6/vendor/patches/pulp-platform/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/include/common_cells -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/include/axi -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/fpga -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc/src -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/BramDwc/deps -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/common -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/synth/common/scripts -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/BramDwc -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/common -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/common/modules -incdir /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/behav/common/include -incdir /home/shc/projects/cva-soc/cva6/common -incdir /home/shc/projects/cva-soc/cva6/common/local -incdir /home/shc/projects/cva-soc/cva6/common/local/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/scripts -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/constraints -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/ariane-ethernet -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi2apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi2apb/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_timer -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_node -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_node/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi_slice -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi_slice/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart/src/vhdl_orig -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb_uart/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/bootrom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/bootrom/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/axi_dw_adapter -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/scripts -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/include/apb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/apb/test -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/.github -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/hal -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/test -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen/topgen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen/topgen/templates -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/src/gpio/util/reggen/reggen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_protocol_checker -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_ila -incdir /home/shc/projects/cva-soc/cva6/corev_apu/fpga/xilinx/xlnx_ila/tcl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if -incdir /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if/src/deprecated -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/prog -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/remote_bitbang -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/unused -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/debug_rom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/doc -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/ci -incdir /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/test -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera/constraints -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/altera/ip -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wb_dcache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wb_dcache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_serdiv -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_serdiv/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_dcache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_dcache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_cva6_icache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_cva6_icache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/dpi -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/wave -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_axi_dcache -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/tb_wt_axi_dcache/hdl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/tb/common -incdir /home/shc/projects/cva-soc/cva6/corev_apu/bootrom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic -incdir /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl -incdir /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/doc -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom/baremetal -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom/linux -incdir /home/shc/projects/cva-soc/cva6/corev_apu/openpiton/bootrom/linux/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/clint -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/lint -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/include/register_interface -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/patches -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/patches/lowrisc_opentitan -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util/topgen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util/topgen/templates -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/util/reggen -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/docs -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/.github -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/.github/workflows -incdir /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/util -incdir /home/shc/projects/cva-soc/cva6/verif/tb/core/tb_components -incdir /home/shc/projects/cva-soc/axi -incdir /home/shc/projects/cva-soc/axi/scripts -incdir /home/shc/projects/cva-soc/axi/src -incdir /home/shc/projects/cva-soc/axi/.gitlab-ci.d -incdir /home/shc/projects/cva-soc/axi/include -incdir /home/shc/projects/cva-soc/axi/include/axi -incdir /home/shc/projects/cva-soc/axi/.ci -incdir /home/shc/projects/cva-soc/axi/doc -incdir /home/shc/projects/cva-soc/axi/doc/svg -incdir /home/shc/projects/cva-soc/axi/.github -incdir /home/shc/projects/cva-soc/axi/.github/workflows -incdir /home/shc/projects/cva-soc/axi/test -incdir /home/shc/projects/cva-soc/obi -incdir /home/shc/projects/cva-soc/obi/src -incdir /home/shc/projects/cva-soc/obi/src/test -incdir /home/shc/projects/cva-soc/obi/include -incdir /home/shc/projects/cva-soc/obi/include/obi -incdir /home/shc/projects/cva-soc/obi/.github -incdir /home/shc/projects/cva-soc/obi/.github/workflows -incdir /home/shc/projects/cva-soc/safety_island/future/axi_obi -incdir /home/shc/projects/cva-soc/safety_island/future/axi_obi/src -incdir /home/shc/projects/cva-soc/rtl/sim -top air_soc /tools/Xilinx/Vivado/2022.2/data/vhdl/src/unisims/unisim_VCOMP.vhd /tools/Xilinx/Vivado/2022.2/data/vhdl/src/unisims/unisim_VPKG.vhd /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/obi/src/obi_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/config_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_soc_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_id_queue.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/top_pkg.sv /home/shc/projects/cva-soc/rtl/src/config/custom_config.sv /home/shc/projects/cva-soc/cva6/core/include/riscv_pkg.sv /home/shc/projects/cva-soc/rtl/src/config/custom_config.sv /home/shc/projects/cva-soc/cva6/core/include/ariane_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/build_config_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/riscv_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/config_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_axi_pkg.sv /home/shc/projects/cva-soc/axi/src/axi_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_axi_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv /home/shc/projects/cva-soc/cva6/core/include/ariane_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/wt_cache_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/std_cache_pkg.sv /home/shc/projects/cva-soc/cva6/core/include/instr_tracer_pkg.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/ecc_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cb_filter_pkg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/ecc_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cb_filter_pkg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_soc_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_axi_soc_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/dm_tb_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_verif_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/top_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/tlul_pkg.sv /home/shc/projects/cva-soc/obi/src/obi_pkg.sv /home/shc/projects/cva-soc/obi/src/test/atop_golden_mem_pkg.sv /home/shc/projects/cva-soc/rtl/sim/ddr3.v /home/shc/projects/cva-soc/rtl/sim/s25fl128s.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_axi_retime.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_axi.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_dfi_seq.v /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_core.v /home/shc/projects/cva-soc/rtl/src/common_cells/fifo_v3.sv /home/shc/projects/cva-soc/rtl/src/common_cells/mem_to_banks_detailed.sv /home/shc/projects/cva-soc/rtl/src/common_cells/stream_fifo.sv /home/shc/projects/cva-soc/rtl/src/soc/air_soc.sv /home/shc/projects/cva-soc/rtl/src/config/custom_config.sv /home/shc/projects/cva-soc/rtl/src/memory/tc_sram_wrapper_cache_techno.sv /home/shc/projects/cva-soc/rtl/src/memory/cache.sv /home/shc/projects/cva-soc/rtl/src/memory/ram_axi.sv /home/shc/projects/cva-soc/rtl/src/memory/ram64.sv /home/shc/projects/cva-soc/rtl/src/memory/axi_synth_mem.sv /home/shc/projects/cva-soc/rtl/src/memory/simpleuart.sv /home/shc/projects/cva-soc/rtl/src/memory/tc_sram.sv /home/shc/projects/cva-soc/rtl/src/memory/bootrom.sv /home/shc/projects/cva-soc/rtl/src/memory/ram.sv /home/shc/projects/cva-soc/rtl/src/memory/ram_obi.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_handshake_fsm.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_demux.sv /home/shc/projects/cva-soc/rtl/src/databus/ram32_obi_adapter.sv /home/shc/projects/cva-soc/rtl/src/databus/obi2wishbone.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_sram_shim_modified.sv /home/shc/projects/cva-soc/rtl/src/databus/obi_demux_mem.sv /home/shc/projects/cva-soc/rtl/src/databus/axi_to_obi_adapter.sv /home/shc/projects/cva-soc/rtl/src/databus/axi_to_dual_obi_adapter.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/dram_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/dram_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/ddr3_dfi_phy.sv /home/shc/projects/cva-soc/rtl/src/peripherals/dram/dram_controller_axi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer_controller_axi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/timer/timer_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/qspi/qspi_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/qspi/qspi_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_controller_obi.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_controller.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_tx.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_rx.sv /home/shc/projects/cva-soc/rtl/src/peripherals/uart/uart_controller_axi.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/test/axi_riscv_atomics_synth.v /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/test/axi_riscv_lrsc_synth.v /home/shc/projects/cva-soc/cva6/core/decoder.sv /home/shc/projects/cva-soc/cva6/core/cvxif_fu.sv /home/shc/projects/cva-soc/cva6/core/cva6_rvfi_probes.sv /home/shc/projects/cva-soc/cva6/core/id_stage.sv /home/shc/projects/cva-soc/cva6/core/ariane_regfile_ff.sv /home/shc/projects/cva-soc/cva6/core/scoreboard.sv /home/shc/projects/cva-soc/cva6/core/mult.sv /home/shc/projects/cva-soc/cva6/core/serdiv.sv /home/shc/projects/cva-soc/cva6/core/cvxif_issue_register_commit_if_driver.sv /home/shc/projects/cva-soc/cva6/core/csr_regfile.sv /home/shc/projects/cva-soc/cva6/core/multiplier.sv /home/shc/projects/cva-soc/cva6/core/controller.sv /home/shc/projects/cva-soc/cva6/core/amo_buffer.sv /home/shc/projects/cva-soc/cva6/core/load_store_unit.sv /home/shc/projects/cva-soc/cva6/core/lsu_bypass.sv /home/shc/projects/cva-soc/cva6/core/axi_shim.sv /home/shc/projects/cva-soc/cva6/core/compressed_decoder.sv /home/shc/projects/cva-soc/cva6/core/instr_realign.sv /home/shc/projects/cva-soc/cva6/core/issue_read_operands.sv /home/shc/projects/cva-soc/cva6/core/cva6_accel_first_pass_decoder_stub.sv /home/shc/projects/cva-soc/cva6/core/load_unit.sv /home/shc/projects/cva-soc/cva6/core/csr_buffer.sv /home/shc/projects/cva-soc/cva6/core/cvxif_compressed_if_driver.sv /home/shc/projects/cva-soc/cva6/core/cva6_rvfi.sv /home/shc/projects/cva-soc/cva6/core/commit_stage.sv /home/shc/projects/cva-soc/cva6/core/cva6_fifo_v3.sv /home/shc/projects/cva-soc/cva6/core/store_unit.sv /home/shc/projects/cva-soc/cva6/core/acc_dispatcher.sv /home/shc/projects/cva-soc/cva6/core/ex_stage.sv /home/shc/projects/cva-soc/cva6/core/fpu_wrap.sv /home/shc/projects/cva-soc/cva6/core/issue_stage.sv /home/shc/projects/cva-soc/cva6/core/zcmt_decoder.sv /home/shc/projects/cva-soc/cva6/core/cva6.sv /home/shc/projects/cva-soc/cva6/core/macro_decoder.sv /home/shc/projects/cva-soc/cva6/core/perf_counters.sv /home/shc/projects/cva-soc/cva6/core/alu.sv /home/shc/projects/cva-soc/cva6/core/ariane_regfile.sv /home/shc/projects/cva-soc/cva6/core/branch_unit.sv /home/shc/projects/cva-soc/cva6/core/store_buffer.sv /home/shc/projects/cva-soc/cva6/core/frontend/btb.sv /home/shc/projects/cva-soc/cva6/core/frontend/instr_scan.sv /home/shc/projects/cva-soc/cva6/core/frontend/frontend.sv /home/shc/projects/cva-soc/cva6/core/frontend/bht.sv /home/shc/projects/cva-soc/cva6/core/frontend/instr_queue.sv /home/shc/projects/cva-soc/cva6/core/frontend/ras.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_axi_adapter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_if_adapter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_cache_subsystem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/axi_adapter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_ctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_mem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_icache_axi_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/miss_handler.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/amo_alu.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_icache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/std_nbdcache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cache_ctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_missunit.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/std_cache_subsystem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/tag_cmp.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/cva6_hpdcache_subsystem.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/wt_dcache_wbuffer.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_ptw.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_tlb.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_mmu.sv /home/shc/projects/cva-soc/cva6/core/cva6_mmu/cva6_shared_tlb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/lint/hpdcache_lint.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_l15_resp_demux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_l15_req_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_resize.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fxarb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_lfsr.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg_initialized.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_demux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_mux.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_upsize.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sync_buffer.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_downsize.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wmask_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_rrarb.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv /home/shc/projects/cva-soc/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv /home/shc/projects/cva-soc/cva6/core/pmp/src/pmp.sv /home/shc/projects/cva-soc/cva6/core/pmp/src/pmp_data_if.sv /home/shc/projects/cva-soc/cva6/core/pmp/src/pmp_entry.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_cast_multi.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_fma_multi.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_noncomp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_fma.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_opgroup_block.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_rounding.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_top.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_divsqrt_multi.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpnew_classifier.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lfsr_8bit.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_xbar.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_filter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/delta_counter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/popcount.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_to_mem.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lfsr.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_detect.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/rstgen.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/gray_to_binary.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/fifo_v3.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lfsr_16bit.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_propagator_rx.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/ecc_encode.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/serial_deglitch.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_intf.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/id_queue.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/ecc_decode.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_arbiter_flushable.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/rstgen_bypass.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/plru_tree.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_demux.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/addr_decode.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_join.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cdc_fifo_2phase.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/sub_per_hash.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/unread.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_omega_net.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/binary_to_gray.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_propagator_tx.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/clk_div.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_fork_dynamic.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/sync.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_mux.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/isochronous_spill_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/sync_wedge.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cdc_2phase.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_fork.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/counter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/exp_backoff.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/edge_propagator.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cb_filter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_delay.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/lzc.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/spill_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/onehot_to_bin.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/cdc_fifo_gray.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/mv_filter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_arbiter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/shift_reg.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/max_counter.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/rr_arb_tree.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/stream_fifo.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/src/fall_through_register.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/stream_arbiter_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/id_queue_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/cdc_2phase_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/synth_bench.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/ecc_synth.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/test/stream_test.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal/counter_properties.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal/fifo_v3_properties.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/common_cells/formal/fall_through_register_properties.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv /home/shc/projects/cva-soc/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_xbar.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/popcount.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_to_mem.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_detect.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/rstgen.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/gray_to_binary.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lfsr_16bit.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_propagator_rx.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/ecc_encode.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/serial_deglitch.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/isochronous_4phase_handshake.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_intf.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/id_queue.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/ecc_decode.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/plru_tree.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_demux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/addr_decode.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_join.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cdc_fifo_2phase.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/sub_per_hash.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/unread.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_omega_net.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/binary_to_gray.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_propagator_tx.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/clk_div.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_fork_dynamic.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/sync.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_mux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/isochronous_spill_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/sync_wedge.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_fork.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/counter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/exp_backoff.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/edge_propagator.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cb_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_delay.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/lzc.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/onehot_to_bin.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cdc_fifo_gray.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/mv_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/shift_reg.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/cc_onehot.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/max_counter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/stream_fifo.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/common_cells/src/fall_through_register.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cdc_dst.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_sim_mem.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_mux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_regs.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_serializer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_iw_converter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_demux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_to_apb.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_mux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_mailbox.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_burst_splitter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_dw_upsizer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_multicut.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_delayer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_dw_converter.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cdc_src.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cdc.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_err_slv.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_demux.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_to_axi.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_cut.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_id_remap.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_join.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_lite_xbar.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_modify_address.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_to_axi_lite.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_id_prepend.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_isolate.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_test.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_intf.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_dw_downsizer.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/axi/src/axi_join.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/tc_pwr.sv /home/shc/projects/cva-soc/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv /home/shc/projects/cva-soc/cva6/common/local/util/hpdcache_sram_wbyteenable_1rw.sv /home/shc/projects/cva-soc/cva6/common/local/util/find_first_one.sv /home/shc/projects/cva-soc/cva6/common/local/util/hpdcache_sram_1rw.sv /home/shc/projects/cva-soc/cva6/common/local/util/tc_sram_wrapper.sv /home/shc/projects/cva-soc/cva6/common/local/util/sram_cache.sv /home/shc/projects/cva-soc/cva6/common/local/util/instr_tracer.sv /home/shc/projects/cva-soc/cva6/common/local/util/sram.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/ariane.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_peripherals.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/ariane_testharness.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/rvfi_tracer.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/axi_intf.sv /home/shc/projects/cva-soc/cva6/corev_apu/bootrom/bootrom.sv /home/shc/projects/cva-soc/cva6/corev_apu/clint/axi_lite_interface.sv /home/shc/projects/cva-soc/cva6/corev_apu/clint/clint.sv /home/shc/projects/cva-soc/cva6/corev_apu/axi_mem_if/src/axi2mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_obi_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dmi_cdc.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/src/dm_sba.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/dp_ram.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/mm_ram.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/tb/boot_rom.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom_one_scratch.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva/dm_sba_sva.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva/dm_top_sva.sv /home/shc/projects/cva-soc/cva6/corev_apu/riscv-dbg/sva/dm_csrs_sva.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_res_tbl.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics.sv /home/shc/projects/cva-soc/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/uart.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/dp_ram.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/mock_uart.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common/core_mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_synch_holdable_driver.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_synch_driver.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/sim_timeout.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_stream_mst.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/clk_rst_gen.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_stream_slv.sv /home/shc/projects/cva-soc/cva6/corev_apu/tb/common_verification/src/rand_id_queue.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_target.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/prim_subreg.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/plic_regmap.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_gateway.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/prim_subreg_ext.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/rv_plic_reg_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/rv_plic/rtl/plic_top.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_test.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_mux.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_demux.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_intf.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/axi_lite_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_uniform.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_to_mem.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/apb_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/periph_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/axi_to_reg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/src/reg_cdc.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_shadow.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_arb.sv /home/shc/projects/cva-soc/cva6/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_ext.sv /home/shc/projects/cva-soc/cva6/verif/tb/core/tb_components/axi_master_connect.sv /home/shc/projects/cva-soc/axi/src/axi_atop_filter.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem_interleaved.sv /home/shc/projects/cva-soc/axi/src/axi_cdc_dst.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem_split.sv /home/shc/projects/cva-soc/axi/src/axi_lite_from_mem.sv /home/shc/projects/cva-soc/axi/src/axi_sim_mem.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem.sv /home/shc/projects/cva-soc/axi/src/axi_lite_mux.sv /home/shc/projects/cva-soc/axi/src/axi_dumper.sv /home/shc/projects/cva-soc/axi/src/axi_chan_compare.sv /home/shc/projects/cva-soc/axi/src/axi_lite_regs.sv /home/shc/projects/cva-soc/axi/src/axi_serializer.sv /home/shc/projects/cva-soc/axi/src/axi_interleaved_xbar.sv /home/shc/projects/cva-soc/axi/src/axi_iw_converter.sv /home/shc/projects/cva-soc/axi/src/axi_demux.sv /home/shc/projects/cva-soc/axi/src/axi_lite_to_apb.sv /home/shc/projects/cva-soc/axi/src/axi_mux.sv /home/shc/projects/cva-soc/axi/src/axi_to_detailed_mem.sv /home/shc/projects/cva-soc/axi/src/axi_from_mem.sv /home/shc/projects/cva-soc/axi/src/axi_lite_mailbox.sv /home/shc/projects/cva-soc/axi/src/axi_burst_splitter.sv /home/shc/projects/cva-soc/axi/src/axi_dw_upsizer.sv /home/shc/projects/cva-soc/axi/src/axi_multicut.sv /home/shc/projects/cva-soc/axi/src/axi_delayer.sv /home/shc/projects/cva-soc/axi/src/axi_to_mem_banked.sv /home/shc/projects/cva-soc/axi/src/axi_rw_split.sv /home/shc/projects/cva-soc/axi/src/axi_xbar_unmuxed.sv /home/shc/projects/cva-soc/axi/src/axi_dw_converter.sv /home/shc/projects/cva-soc/axi/src/axi_rw_join.sv /home/shc/projects/cva-soc/axi/src/axi_cdc_src.sv /home/shc/projects/cva-soc/axi/src/axi_cdc.sv /home/shc/projects/cva-soc/axi/src/axi_err_slv.sv /home/shc/projects/cva-soc/axi/src/axi_lite_demux.sv /home/shc/projects/cva-soc/axi/src/axi_lite_to_axi.sv /home/shc/projects/cva-soc/axi/src/axi_throttle.sv /home/shc/projects/cva-soc/axi/src/axi_cut.sv /home/shc/projects/cva-soc/axi/src/axi_id_remap.sv /home/shc/projects/cva-soc/axi/src/axi_bus_compare.sv /home/shc/projects/cva-soc/axi/src/axi_lite_join.sv /home/shc/projects/cva-soc/axi/src/axi_lite_xbar.sv /home/shc/projects/cva-soc/axi/src/axi_lite_dw_converter.sv /home/shc/projects/cva-soc/axi/src/axi_slave_compare.sv /home/shc/projects/cva-soc/axi/src/axi_modify_address.sv /home/shc/projects/cva-soc/axi/src/axi_lfsr.sv /home/shc/projects/cva-soc/axi/src/axi_to_axi_lite.sv /home/shc/projects/cva-soc/axi/src/axi_id_prepend.sv /home/shc/projects/cva-soc/axi/src/axi_isolate.sv /home/shc/projects/cva-soc/axi/src/axi_fifo.sv /home/shc/projects/cva-soc/axi/src/axi_test.sv /home/shc/projects/cva-soc/axi/src/axi_xbar.sv /home/shc/projects/cva-soc/axi/src/axi_intf.sv /home/shc/projects/cva-soc/axi/src/axi_dw_downsizer.sv /home/shc/projects/cva-soc/axi/src/axi_join.sv /home/shc/projects/cva-soc/axi/src/axi_demux_simple.sv /home/shc/projects/cva-soc/axi/src/axi_xp.sv /home/shc/projects/cva-soc/axi/test/axi_synth_bench.sv /home/shc/projects/cva-soc/obi/src/obi_sram_shim.sv /home/shc/projects/cva-soc/obi/src/obi_mux.sv /home/shc/projects/cva-soc/obi/src/obi_intf.sv /home/shc/projects/cva-soc/obi/src/obi_demux.sv /home/shc/projects/cva-soc/obi/src/obi_cut.sv /home/shc/projects/cva-soc/obi/src/obi_rready_converter.sv /home/shc/projects/cva-soc/obi/src/obi_xbar.sv /home/shc/projects/cva-soc/obi/src/obi_err_sbr.sv /home/shc/projects/cva-soc/obi/src/test/obi_test.sv /home/shc/projects/cva-soc/obi/src/test/obi_sim_mem.sv /home/shc/projects/cva-soc/obi/src/test/obi_asserter.sv /home/shc/projects/cva-soc/safety_island/future/axi_obi/src/axi_to_obi.sv /home/shc/projects/cva-soc/safety_island/future/axi_obi/src/obi_to_axi.sv /home/shc/projects/cva-soc/safety_island/future/axi_obi/src/axi_to_detailed_mem_user.sv /home/shc/projects/cva-soc/vivado/cva_soc_zc706/cva_soc_zc706.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/glbl.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/OBUFDS.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IOBUFDS.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/OSERDESE2.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/ISERDESE2.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IOBUF.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IDELAYE2.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IDELAYCTRL.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/BUFG.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/IBUFDS.v /tools/Xilinx/Vivado/2022.2/data/verilog/src/unisims/MMCME2_ADV.v

  • in reply to Celluk

    Nothing helped until now in terms of flags as I indicated in my previous response, I even tried -xmvlogargs "-update" and -xmvlogargs "-XMWARN DLCSMD" flags but didn't work again.

    However finally, I solved the errors by tracing *W,RECOME warnings to remove duplicates manually from the compilation list. Xcelium is the fastest sim tool for SV simulation I have used so far and that's why it is appealing however these kind of non-error errors takes away me from to use it effectively. I understand it is for fail safety but sometimes annoying if we cannot disable them. Please take it as a feedback and add a flag such as -override for future versions if possible.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.