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PSL endpoints and ended()

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I need to write a property that states if conditon A occurs then SeqA or SeqB must have occured.

The PSL built-in ended() is not supported in IFV 5.7-s5.  So, I can't do either of these:
always {A} |-> {ended(SeqA) | ended(SeqB)}
 
never (A & ~(ended(SeqA) | ended(SeqB))

Also, I get this error when calling SeqA and SeqB endpoints.
endpoint SeqA ...
endpoint SeqB ...

always {A} |-> {SeqA | SeqB}
                   |
"Endpoints and sequences are illegal as verilog operands."

Does anyone have another idea how this can be done?

Thanks,

Ross


Originally posted in cdnusers.org by weberrm
Parents

  • I think that the "endpoint" in PSL has been dropped from the latest IEEE standard. We have it in our parser for backwards compatibility.

    The "ended()" function from the PSL standard takes a sequence as a parameter and returns a boolean as a result. Here is the code from a sample Vunit file that I put together to observe the behavior when support for the ended() function first came out in IUS 5.7.

    vunit testended ( testit ) {
    default clock = posedge clk;
    sequence abc_seq = { a; b; c }@(posedge clk);
    p_ended: assert always { ended(abc_seq) } |=> { d };
    endpoint abc_ep = { a; b; c };
    p_endpt: assert always abc_ep -> next d;
    always @(posedge ended(abc_seq)) $display($time,,"a;b;c has ended");
    wire y;
    assign y = ended(abc_seq);
    }

    So, you can use "ended()" in a property or sequence and pass it a sequence name. You can use it to affect the HDL behavior. The rest of the discussion here seems to be around syntax issues, making sure that you use sequences where sequences are legal and booleans where they are legal. Keeping you parentheses and braces correct can be confusing, but it is necessary.


    Originally posted in cdnusers.org by TAM
Reply

  • I think that the "endpoint" in PSL has been dropped from the latest IEEE standard. We have it in our parser for backwards compatibility.

    The "ended()" function from the PSL standard takes a sequence as a parameter and returns a boolean as a result. Here is the code from a sample Vunit file that I put together to observe the behavior when support for the ended() function first came out in IUS 5.7.

    vunit testended ( testit ) {
    default clock = posedge clk;
    sequence abc_seq = { a; b; c }@(posedge clk);
    p_ended: assert always { ended(abc_seq) } |=> { d };
    endpoint abc_ep = { a; b; c };
    p_endpt: assert always abc_ep -> next d;
    always @(posedge ended(abc_seq)) $display($time,,"a;b;c has ended");
    wire y;
    assign y = ended(abc_seq);
    }

    So, you can use "ended()" in a property or sequence and pass it a sequence name. You can use it to affect the HDL behavior. The rest of the discussion here seems to be around syntax issues, making sure that you use sequences where sequences are legal and booleans where they are legal. Keeping you parentheses and braces correct can be confusing, but it is necessary.


    Originally posted in cdnusers.org by TAM
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