Stats

  • Locked Locked
  • Replies 1
  • Subscribers 64
  • Views 13081
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

verification of connectivity at top-level

archive

Hi,

How do you verify the connectivity at the top-level? How to make sure a user has not messed up a[m:n] with a[n:m]? Do you generally use simulation and toggle coverage to verify this or formal?

Your insight will be appreciated.

Regards,
Sibil


Originally posted in cdnusers.org by Sibil

  • Hi Sibil,

    Let's take an example:
    - Assume the top level module is called top
    - Assume top instantiates blocks 'A' and 'B'
    - Assume blocks 'A' and 'B' have inputs data_in[63:0] and data_out[63:0]
    - Assume at the top level data_out from block A should be connected to data_in of block B

    You could write an assertion that checks that "top.data_out[63:0] is equal to top.data_in[63:0]". If you feed this assertion to IFV it will either be trivially true of trivially false; runtime should be very quick (should be approximately equal to the time it takes to read the design into the tool).

    Regards,
    Amir


    Originally posted in cdnusers.org by amirl

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.