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Property transformations

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There are many ways of specifying the same behaviour by writing a variety of PSL/SVA assertions.
For example, a specification says that after req the grant should come within 5 clock cycles. I wrote it
like

// psl property P1:  (always ( req ) -> {!gnt[*0:4] ; gnt } ) @ (posedge clk);

how do I write this same property using the never form ?
Can this behaviour be written in any other form ? What are the advantages disadvantages of these
different forms.

TG


Originally posted in cdnusers.org by TG
Parents

  • Oops, Axels is right. I read the original sequence as if it used the non-overlapping implication operator |=>, while in fact it appears as if it was supposed to be using the overlapping form of that operator |->.


    Originally posted in cdnusers.org by TAM
Reply

  • Oops, Axels is right. I read the original sequence as if it used the non-overlapping implication operator |=>, while in fact it appears as if it was supposed to be using the overlapping form of that operator |->.


    Originally posted in cdnusers.org by TAM
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