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N unique stable data vectors

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Working off the concept that a property like the following causes a formal tool to try all values of the stable_data wire...

wire [W-1:0] stable_data;
//psl assume_stable_data: assume always(stable(stable_data))@(posedge clk);

Is there a way to generate N stable_data vectors and at the same time guarantee that at any one time the data in them is unique.

If I just wanted 2 vectors I might do something like the following:

wire [W-1:0] stable_data0,stable_data1;
//psl assume_stable_data0: assume always(stable(stable_data0))@(posedge clk);
//psl assume_stable_data1: assume always(stable(stable_data1))@(posedge clk);

//psl assume_unique_data: assume always(
// stable_data0!=stable_data1
//)@(posedge clk);

Extending this to N vectors seems troublsome.  Any ideas?

One might also ask how to fill a NxW array with unique stable data.

Just for clarification, the fact that the data is stable isn't really a necessary component of this question.  I am mainly just wondering how I could easily generate N unique vectors of data.  It's just that data like this is usually stable in proofs.

Thanks,

Ross


Originally posted in cdnusers.org by weberrm
Parents

  • Below is a more elegant (and better) solution than what I posted above.

    I just used some verilog to determine when the data slices were equal and wrote an assumption to prevent the signal from ever becoming true.  I also added a stable assumption that is only needed if you want the data to be stable throughout a sequence.

    module unique_stable_data
    #(
    parameter
    N=4,
    DATA_W=5
    )
    (
    input clk,
    input [(N*DATA_W)-1:0] data
    );

    reg data_eq;
    integer i,j;
    always @* begin
      data_eq=1'b0;
      for(i=0;i < N-1;i=i+1) begin
        for(j=i+1;j < N;j=j+1) begin
          data_eq = data_eq | (data[i*DATA_W+:DATA_W]==data[j*DATA_W+:DATA_W]);
        end
      end
    end

    //psl assume_data_ne: assume never(data_eq)@(posedge clk);


    // If the data needs to be stable
    //psl assume_stable_data: assume always(
    //  stable(data)
    //)@(posedge clk);

    endmodule


    Originally posted in cdnusers.org by weberrm
Reply

  • Below is a more elegant (and better) solution than what I posted above.

    I just used some verilog to determine when the data slices were equal and wrote an assumption to prevent the signal from ever becoming true.  I also added a stable assumption that is only needed if you want the data to be stable throughout a sequence.

    module unique_stable_data
    #(
    parameter
    N=4,
    DATA_W=5
    )
    (
    input clk,
    input [(N*DATA_W)-1:0] data
    );

    reg data_eq;
    integer i,j;
    always @* begin
      data_eq=1'b0;
      for(i=0;i < N-1;i=i+1) begin
        for(j=i+1;j < N;j=j+1) begin
          data_eq = data_eq | (data[i*DATA_W+:DATA_W]==data[j*DATA_W+:DATA_W]);
        end
      end
    end

    //psl assume_data_ne: assume never(data_eq)@(posedge clk);


    // If the data needs to be stable
    //psl assume_stable_data: assume always(
    //  stable(data)
    //)@(posedge clk);

    endmodule


    Originally posted in cdnusers.org by weberrm
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