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verifying clock divider

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Hello,

How do you verify your clock divider logic, generally? Would you recommend assertions to verify clock dividers? Would this be a good candidate for formal verification?

Any info will be appreciated.


Regards,
Amir


Originally posted in cdnusers.org by Sibil

  • Hi Amir:

    I have used IFV with a clock divider logic before. It works out quite well for me. I remember what we have done with that module was to check based on certain control signals, output clock should be divided down accordingly. The assertions are like given the control, for how many rising edge of the input clock, you are expecting a rising edge of the divided down clock. For us, all assertions got proven within minutes. However in general, the performance depends on how big your divider logic is.

    Regards,

    Bin


    Originally posted in cdnusers.org by binju

  • Hi,

    I have written a simple formal verification IP for clock divider. I'm attaching it to this email. It might help somebody.

    Regards,
    Amir


    Originally posted in cdnusers.org by Sibil

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