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for/generate

archive

I apologize for deleting this thread - I was attempting to fix the code issue on the first post which was skewing the formatting of the entire thread.

I learned that i cannot delete the top post in a thread without deleting all the replies.

I will attempt to regenerate the thread now.

Administrator

Initial post by alexsieh

The first code is : 

module edge_detector(sign_i, // Input of the Edge Detector
rise_o, // Rising Edge Output of the Edge Detector
fall_o, // Falling Edge Output of the Edge Detector
clk, // clock
rst_b, // Synchronous Reset
);

//--------------------- Parameters Declaration ---------------------------------
parameter SIZE = 1;

//-------------------- Inputs Declaration --------------------------------------
input [SIZE-1:0]sign_i;
input clk;
input rst_b;


//---------------------- Outputs Declaration -----------------------------------
output [SIZE-1:0]rise_o;
output [SIZE-1:0]fall_o;

//------------------- Types Declaration ----------------------------------------
wire clk;
wire rst_b;
wire [SIZE-1:0]sign_i;
wire [SIZE-1:0]rise_o;
wire [SIZE-1:0]fall_o;
reg [SIZE-1:0]sign_i_syn;
reg [SIZE-1:0]out_ff2;
wire [SIZE-1:0]out_xor;

genvar i; // auxiliar variable to generate

generate for(i=0;i begin
//------------------------ Sequential Part ------------------------------------ 

always @(posedge clk)
begin
if (!rst_b)
begin

sign_i_syn[i]<=1'b0; //If reset occured clear flip flops

out_ff2<=1'b0; 

end //if(!rst) 

else 
begin 

sign_i_syn[i]<= sign_i[i]
//Transform the entering signal in synchronous 

out_ff2 [i] <= sign_i_syn[i]
//Update the second ff output value

end //else 
end //always @(posedge clk)


//-------------------------------- Combinational Part ------------------------ 

assign out_xor[i] = (sign_i_syn[i] ^ out_ff2[i]); 
// keeps the output from the xor in 1 for 1 period of clock in the rise or fall

assign rise_o[i] = (sign_i_syn[i] & out_xor[i]); 
// if the entering sinal has high level and the pulse in the xor output 
// represents a rising edge

assign fall_o[i] = ~(sign_i_syn[i] | ~out_xor[i]); 
// if the entering sinal has low level and the pulse in the xor output 
// represents a falling edge

end // for (generate) 
endgenerate


The Second: 
for i in {0,1,2} generate
begin: check1
{// psl check_init: assert (!value[i]) @rose(resetn);
end
endgenerate;


The third: 
for i in {0,1,2} generate
begin: check1
{//psl RISING: assert always ( rose(sign_i?]) -> next PULSE(rise_o) 
// abort !rst_b)
// report "Rising Edge Failed " severity warning;
//@fell(clk); 
end
endgenerate;


The fourth: 
generate for(i=0;i begin: Rise
//psl RISING: assert always ( rose(sign_i?]) -> next PULSE(rise_o) 
// abort !rst_b)
// report "Rising Edge Failed " severity warning;
//@fell(clk); 
end
endgenerate


The sixth: probe -create -assertions -transaction -waveform -name RISING edge_detector_tb.edge_detector.Rise?].RISING Thanks and sorry about that,


Originally posted in cdnusers.org by Administrator

  • Reply from TAM:

    I tried doing this using IUS 6.11 and everything seemed to work fine for me. I did have to interpolate a little since the code that I cut-and-pasted from this thread needed some massaging to compile.

    Your original syntax problem appears to be because you put some PSL code into your HDL model without using the "// psl" comment prefix. So the Verilog parser was trying to parse the PSL as if it was Verilog. If the Cadence examples have code without the PSL prefix in them, then I think that they are wrong. Can you point me to the document you were referencing?

    Secondly, using a Verilog loop-generate seems to work fine. If anyone can tell me how to upload a 'tar.gz' file to this forum, I could post an example that takes everything thru the process and displays the assertion as a transaction in a waveform window at the end. Personally, I think it is a little too much code to post in-line.


    Originally posted in cdnusers.org by Administrator

  • reply from TAM:

    Here is a small example that, if you run it using IUS 6.11, should pop up a waveform window with your assertion displayed as a transaction.


    Originally posted in cdnusers.org by Administrator
    pslgen[1].tar.gz

  • Thx TAM,
    Seens that my problem is in the settings of the simvision. I am currently studying the file asserts.svcf to see what is missing in my configuration.

    I was using the comand > ncverilog -f run_edgedetector.f  in the prompt with the file run_edgedetector that I placed in the attached file. And the tcl file probes_edgedetector.tcl .

    But seens that this asserts.svcf files has fundamental configurations that makes this probes work. First I tought the problem was cause I am using IUS 5.8, but now I was able to make your files work.


    About the second code in my post, sorry if I did not undestood right, but you mean that it suposed to work but should be writte like this?

    //psl for i in {0,1,2} generate
    // begin: check1
    {// psl check_init: assert (!value[i]) @rose(resetn);
    // end
    //endgenerate;

    The document I was referencing was abvwrite.pdf (Assertion Writing Guide Product Version 5.83 November 2006) page 67.

    Thanks for the help,


    Originally posted in cdnusers.org by alexsieh
    edge_detector_to_send.tar.gz

  • (I just got back from my vacation. It was great! Thank-you-very-much. :-))

    I looked up that code fragment in the abvwrite.pdf file and it isn't even close to being legal Verilog or PSL syntax. It seems to be some combination of the two. Here is how the code should look in PSL using the 'forall' operator:

      // psl sequence P(boolean a) = { a; !a };
      // psl R: assert forall i in { 0 }:
      //   always ( rose(sign_i[i]) -> next P(rise_o) abort !rst_b )
      //       report "Rising Edge Failed " severity warning;  
      //       @rose(clk); 

    My earlier example shows how to replicate the property using a Verilog for-generate loop:

      generate for(i=0;i < SIZE; i=i+1)
       begin: Rise  
         // psl sequence PULSE(boolean a) = { a; !a };
         // psl RISING: assert always ( rose(sign_i[i]) -> next PULSE(rise_o)   
         //      abort !rst_b)  
         //      report "Rising Edge Failed " severity warning;  
             //      @rose(clk);  
       end
     endgenerate

    I guess it would be your choice as to which syntax you want to use.


    Originally posted in cdnusers.org by TAM

  • Oops. My previous post has legal syntax for the forall operator, but it only creates one copy of the assertion. The forall replication should look like this:

    // psl R: assert forall i in { 0:SIZE-1 }:


    Originally posted in cdnusers.org by TAM

  • Thx TAM,
    This forall sintax worked for me now :) The only think that still do not work is the probe, with your .tcl and .svcf it works, but I can not find which configuration make it works. So I tried to use only nclaunch and mouse commands in the assertion browser to create the probes. But when I click in creat probe with the transaction configuration it show Probe Created but it never appers in the waveform window. That's so weird, the same error that I have with my .tcl and .svcf file. I am studying this .tcl and .svcf files and formats for about 5 days and still have no clue what is happening. My guess is that the problem is either with the version IUS5.8 or the database, but as long as I have created through assertion browser, I see no reason to the database be missconfigured. The good news is that soon we will be updating to IUS6.1, maybe it will start working. Have you ever heard about a similar problem?

    Thanks again,
    Alex Sieh

    Ps: That's good to heard about your vacation :) Next time, come to Brazil :)


    Originally posted in cdnusers.org by alexsieh

  • I don't think it is a version issue, so I would expect 6.1 to work (or not work) for you in the same manner. Faced with an issue like this, I would debug it by bringing up my simulation and creating the probe as you've tried. Then I'd use the File->Save Command Script option to write out my environment. Then I'd compare the settings saved in that file with the settings in the file that I sent that is working for you. It could be tedious, but sometimes the difference is obvious.


    Originally posted in cdnusers.org by TAM

  • Hey TAM!
    Good news! After days and days in this problems, I was able to make it works!
    Your last tip was exacly what I was doing currently. The save script .svcf had two main diferences.

    1- The access to the data base was:
    #
    # Simulator
    #

    database require simulator -hints {
    simulator "ncsim -gui -cdslib /mnt/auto/titania/usuarios/tabarani/Blocos/cds.lib -logfile ncsim.log -errormax 15 -status worklib.edge_detector_tb:module -input restore.tcl"
    }

    I have changed to:

    #
    # databases
    #
    database require waves -hints {
    file ./EdgeDetector.shm/EdgeDetector.trn
    file ./EdgeDetector.shm/EdgeDetector.trn
    }

    And it was not including the probe in the .svcf script, it was only:
    set id [waveform add -signals [list simulator::edge_detector_tb.SIZE \
    simulator::edge_detector_tb.clk \
    {simulator::edge_detector_tb.fall[0:0]} \
    {simulator::edge_detector_tb.rise[0:0]} \
    simulator::edge_detector_tb.rst_b \
    {simulator::edge_detector_tb.sign_i[0:0]} ]]

    And I have changed to:
    set id [waveform add -signals [list {edge_detector_tb.clk} \
    {edge_detector_tb.fall} \
    {edge_detector_tb.rise} \
    {edge_detector_tb.rst_b} \
    {edge_detector_tb.sign_i} \
    {edge_detector_tb.edge_detector.\Rise[0] .tr_RISING} \
    {edge_detector_tb.edge_detector.\Fall[0] .tr_FALLING} \
    {edge_detector_tb.fail_probe_1} ]]


    Seens to me that the IUS5.8 is not dealing properly with this generate structure and probes, changing the script it works fine :-)

    Thanks,
    Alex Sieh

    Ps: And you are right it was tedious :)


    Originally posted in cdnusers.org by alexsieh

  • I was expecting to see a difference in one of the 'preferences' settings. Just updating the restore script's probe command doesn't help you the next time that you want to see an transaction interactively. You may want to open a Service Request with Cadence to ask about what might be happening. Trying to debug it in this forum wouldn't be very interesting to very many people (and isn't perhaps the most efficient way to do it either). Good luck!


    Originally posted in cdnusers.org by TAM

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