Keep internal signals' names after synthesis

When I synthesize my designs, RTL compiler exchanges the internal signals' names for random ones. Does anyone know if there is a way to keep the internal signals' names? Or, is there a way to map the old names to the new ones? I'll try to explain my problem in a better way. I'm using PSL to verify the functioning of my design and I map internal signals to external ones (using ncmirror) in order to be able to evaluate them in PSL. When I'm using RTL that's ok, but when I have to verify the generated netlist, RTL compiler keeps the port's names but changes the name of some signals. For example, if I map a signal which name is tmod_s in my PSL, after synthesis this signal's name is changed for something like n_25 and my PSL does not work anymore. I've tried the following command before elaboration but I didn't have success: set_attr preserve true -net I've tryied to preserve the signal count_enable_s which is set as following: count_enable_s