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Keep internal signals' names after synthesis

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When I synthesize my designs, RTL compiler exchanges the internal signals' names for random ones. Does anyone know if there is a way to keep the internal signals' names? Or, is there a way to map the old names to the new ones? I'll try to explain my problem in a better way. I'm using PSL to verify the functioning of my design and I map internal signals to external ones (using ncmirror) in order to be able to evaluate them in PSL. When I'm using RTL that's ok, but when I have to verify the generated netlist, RTL compiler keeps the port's names but changes the name of some signals. For example, if I map a signal which name is tmod_s in my PSL, after synthesis this signal's name is changed for something like n_25 and my PSL does not work anymore. I've tried the following command before elaboration but I didn't have success: set_attr preserve true -net I've tryied to preserve the signal count_enable_s which is set as following: count_enable_s


Originally posted in cdnusers.org by mvetromille
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  • Hi Melissa,
    This is more of a RTL compiler question and perhaps you should ask in the Digital IC forum for synthesis experts comments.

    As Joerg mentioned, it will be a good idea to write PSL on ports only - especially for those properties expected to be reused at GLS.
    We make some of these recommendations in our PSL book (see: www.systemverilog.us).

    Another relevant guideline was to use only Sequential nodes in your PSL code - in your case you are lucky that the combinatorial nodes are still present. We have seen cases where the whole logic gets optimized and the signal is lost.

    We at CVC have a half-a-day workshop on "ABV beyond RTL" that touches upon this topic very extensively, provides examples on how to handle common synthesis optimizations (like bit blasting etc.). It also provides template flow on how to use an equivalence checker to automate this kind of mapping.

    Perhaps Conformal can provide a flow for this if you work closely with you Cadence AE.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
Reply

  • Hi Melissa,
    This is more of a RTL compiler question and perhaps you should ask in the Digital IC forum for synthesis experts comments.

    As Joerg mentioned, it will be a good idea to write PSL on ports only - especially for those properties expected to be reused at GLS.
    We make some of these recommendations in our PSL book (see: www.systemverilog.us).

    Another relevant guideline was to use only Sequential nodes in your PSL code - in your case you are lucky that the combinatorial nodes are still present. We have seen cases where the whole logic gets optimized and the signal is lost.

    We at CVC have a half-a-day workshop on "ABV beyond RTL" that touches upon this topic very extensively, provides examples on how to handle common synthesis optimizations (like bit blasting etc.). It also provides template flow on how to use an equivalence checker to automate this kind of mapping.

    Perhaps Conformal can provide a flow for this if you work closely with you Cadence AE.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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