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what is dynamic verification?

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hi,
can anybody let me know dynamic verification in verilog and information about the coverage probes in verilog.


Originally posted in cdnusers.org by thirmalrao

  • Hello:

    Dynamic verification you mentioned should refer to "Testbench Simulation". Designers can verify the functional correctness of DUV (Design Under Verification) by using dynamic simulation environment (including drivers, monitors, BFMs, reference models, etc) along with testbenches.

    There're several different coverages can evaluated for design/environment in verilog: code coverage (including line coverage, toggle coverage, FSM state/transition coverage, branch coverage, etc.), functional coverage (assertion based), stimulus coverage, etc.

    You can find more details in those books talking about Verilog HDL or workshops provided by Cadence.

    Darrow


    Originally posted in cdnusers.org by darrowchu

  • Thank you Darrow


    Originally posted in cdnusers.org by thirmalrao

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