• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. How to check data integrity with assertions?

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 65
  • Views 16808
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to check data integrity with assertions?

archive
archive over 17 years ago

I am verifying a bus system. Apart from verifying simple point to point connectivity checks, I am also planning to do a data integrity check. What is the best way to do that with assertions in a pure formal environment?
If I write a set of all-0s and all-1s and then read it back, does that do a proper integrity check? Please suggest any better way to do this.


Originally posted in cdnusers.org by bijitm
  • Cancel
  • archive
    archive over 17 years ago

    Hi bijitm,

    there is an example for data integrity in a fifo: If data enters the FIFO then “sooner or later” the same data exits the FIFO:

    output_data_integrity : assert forall dvalue in {0:255} :
    always ( (push && data_in == dvalue) ->
    eventually! (pop && data_out == dvalue));

    Two key aspects here are liveness (eventually) and non deterministic constants (forall). For a bus system this concept is also applicable, but maybe you are able to predict exactly when the output should show the data coming in (e.g. same or next cycle instead of eventually). The "push" in a bus system represents the control signal condition indicating a transfer coming in and the "pop" goint out.

    In fully symmetric datapath a valid abstraction is to use only one bit instead of the full data vector, that can reduce complexity for the formal prove.

    Joerg.


    Originally posted in cdnusers.org by jmueller
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • archive
    archive over 17 years ago

    Hi!

    Below is anoter way to do it without the forall.

    logic [W-1:0] dvalue;
    assume_stable_dvalue: assume always(stable(dvalue))@(posedge clk);

    assert_data_integrity: assert always(
      push & (data_in==dvalue) ->eventually!
      pop & (data_out==dvalue)
    )@(posedge clk);


    This technique uses a non-deterministic constant, dvalue, which takes on and holds all values for the proof.

    Depending on the tool version you are using I've had clocking problems with the forall.  Also, to protect all values, instead of 255 you would need something like ((2**W)-1) in the forall solution.  The forall solution does have the advantatge of working in simulation.  However, the questioner said the verification would be done formally.


    Originally posted in cdnusers.org by weberrm
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information