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System Verilog ... for dummies

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I am planning to use System verilog - not System C - for writing a test for a SOC ASIC. I am looking at Cadence online documentation and I can find just ncverilog and systemc, not system verilog. This confuses me: I do not want to go that far with System C, so I like System Verilog which let me have a resonable learrning curve: I still have the ability to either design synthesizeable logic with verilog 2001 AND write mid-to-high level verification code in the system verilog without referring any object code - either SystemC or C++ - in the simulation model, just compiling everything.

Question is: how do I compile Sytem verilog in a Cadenc e simulation environment? I acannot find the keywords 'system verilog' in the cdsdoc engine either ...

many thanks in advance


Originally posted in cdnusers.org by marco.stanzani
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  • Hi Marco,
    Cadence has also been developing a SystemVerilog testbench methodology, called the "Universal Reuse Methodology" (uRM), as part of the complete Incisive Plan to Closure Methodology development effort.  The methodology includes documentation, and code examples.  If you can send me an email (stellfox@cadence.com), I can put you in touch with an AE who can show you how to leverage the uRM methodology.  This should make it much easier for you to come up to speed on how to use SystemVerilog for building testbenches.  It also includes examples on how to connect SystemVerilog verfication components to e verification components.

    Regards,
    Mike


    Originally posted in cdnusers.org by stellfox@cadence.com
Reply

  • Hi Marco,
    Cadence has also been developing a SystemVerilog testbench methodology, called the "Universal Reuse Methodology" (uRM), as part of the complete Incisive Plan to Closure Methodology development effort.  The methodology includes documentation, and code examples.  If you can send me an email (stellfox@cadence.com), I can put you in touch with an AE who can show you how to leverage the uRM methodology.  This should make it much easier for you to come up to speed on how to use SystemVerilog for building testbenches.  It also includes examples on how to connect SystemVerilog verfication components to e verification components.

    Regards,
    Mike


    Originally posted in cdnusers.org by stellfox@cadence.com
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