Parameterized classes

Hi,

I was wondering if/when parameterized classes were going to be supported?  I seem to be getting errors in 5.7-s1 of seemingly legal syntax according to the 3.1a System Verilog LRM section 11.23.

class class_test #(int W=5);
                     |
ncvlog: *E,NULLPP (test.v,3|21): empty/illegal list of parameters [12.1(IEEE-2001)].

The error seems to be referring to the 12.1 Modules section of the Verilog 2001 LRM.

SV 3.1a LRM excerpt:
11.23 Parameterized classes
It is often useful to define a generic class whose objects can be instantiated to have different array sizes or data
types. This avoids writing similar code for each size or type, and allows a single specification to be used for
objects that are fundamentally different, and (like a templated class in C++) not interchangeable.
The normal Verilog parameter mechanism is used to parameterize a class:
class vector #(int size = 1);
bit [size-1:0] a;
endclass
Instances of this class can then be instantiated like modules or interfaces:
vector #(10) vten; // object with vector of size 10
vector #(.size(2)) vtwo; // object with vector of size 2
typedef vector#(4) Vfour; // Class with vector of size 4