• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. Overriding constraints

Stats

  • Locked Locked
  • Replies 5
  • Subscribers 64
  • Views 15253
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Overriding constraints

archive
archive over 19 years ago

Using the example below, how can I override the constraints of classes A and B on an instance by instance basis?

For instance, let's say I wanted a1's constraint of VarA0 to be VarA0 > 3 and b1's constraint of  VarB1 to be VarB1

Thanks!


module test();
  class A;
    rand bit [3:0] varA0;
    rand bit [3:0] varA1;

    constraint c0 { varA0 > 1; }
    constraint c1 { varA1 > 2; }
  endclass

  class B;
   rand bit [3:0] varB0;
   rand bit [3:0] varB1;

   constraint c0 { varB0 > 1; }
   constraint c1 { varB1 > 2; }
 endclass

  A a0=new;
  A a1=new;
  B b0=new;
  B b1=new;

initial begin
  if (a0.randomize()==0) begin
    $display("error!");
  end
  if (a1.randomize()==0) begin
    $display("error!");
  end
  if (b0.randomize()==0) begin
    $display("error!");
  end
  if (b1.randomize()==0) begin
    $display("error!");
  end
  $display("a0.varA0=%d",a0.varA0);
  $display("a0.varA1=%d",a0.varA1);
  $display("a1.varA0=%d",a1.varA0);
  $display("a1.varA1=%d",a1.varA1);
  $display("b0.varB0=%d",b0.varB0);
  $display("b0.varB1=%d",b0.varB1);
  $display("b1.varB0=%d",b1.varB0);
  $display("b1.varB1=%d",b1.varB1);
end   
 
endmodule




Originally posted in cdnusers.org by weberrm
  • Cancel
Parents
  • archive
    archive over 17 years ago

    Hi,
    I have written a brief article on soft constraints:
    http://www.aceverification.com/Soft%20Constraints%20for%20SystemVerilog.pdf
    Also, you can download Ace Verification's soft constraints for SV at the following link: http://www.aceverification.com/softconstraints_pkg.htm

    Akiva


    Originally posted in cdnusers.org by Akiva
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • archive
    archive over 17 years ago

    Hi,
    I have written a brief article on soft constraints:
    http://www.aceverification.com/Soft%20Constraints%20for%20SystemVerilog.pdf
    Also, you can download Ace Verification's soft constraints for SV at the following link: http://www.aceverification.com/softconstraints_pkg.htm

    Akiva


    Originally posted in cdnusers.org by Akiva
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information