Need help regarding interface usage in Systemverilog...

Hi All,

I'm having problem when i used the interface declaration in module. Pls see the error i got.
My UART DUT is a verilog module.

ncelab: *E,CUINMD (./sips_uart_bfm.sv,13|43): An interface connection must be connected to a Verilog parent (sips_uart_bfm).

module sips_uart_bfm(sips_uart_bfm_if  bfm_if, sips_uart_uart_if  uart_if, input reset,input clock);

This is an incompatible connection.  A Verilog interface must be connected
       to a port of a Verilog instance.  All other languages and connection
       types are disallowed.

Pls suggest me how to go about this.

Thanks & Regards,
Prabhu Kumar