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Poor SystemVerilog Support in NC?

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I have tried to use SystemVerilog in NC and I have noticed that several basic features of SV are not (yet) supported. I am not speaking of exotic stuff, but things that have been supported by the two big competitors for quite some time now.

For example, the string datatype (although I have been told that strings will be supported in the next release).

But what's much worse is that the DPI implementation is seriously limited, it seems that time consuming tasks cannot be exported to C. Unless I'm missing something - which is entireliy possible - this renders the DPI interface completely useless for creating transactors.

module dpitest (input CLK);
  export "DPI-C" task sv_idle;
  task sv_idle(input int cycles);
     repeat (cycles) @(posedge CLK);
  endtask
endmodule

ncelab: 05.81-p002: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
ncelab: *E,TSKTIM: Exported task sv_idle cannot consume time during simulation.

How are other readers of this forum implementing transactors that are driven from the C side? How could one use SystemC for verification if there is no way to get transactions through the DPI interface?

chm.


Originally posted in cdnusers.org by chm
Parents

  • Hi Chm,

    Sorry, I was not able to reply to your mail earlier.

    Thinking a bit more about your problem, I was wondering if the C portion of your testbench is simulation clock aware at all? If not, how hard would it be for you to create a time aware layer in your C code?

    The solution, I had in mind was to run your C application as an SC_THREAD in systemC. You can make the SC_THREAD sensitive to the clock in verilog design. SC_THREAD in systemC can consume time by waiting on event. You can therefore modify your read and write methods to be something like this:

    while (read_not_done_in_verilog)
    {
    wait until next clock edge;
    if (read_done_in_verilog)
    {

    }
    }


    Originally posted in cdnusers.org by nitin_sharma
Reply

  • Hi Chm,

    Sorry, I was not able to reply to your mail earlier.

    Thinking a bit more about your problem, I was wondering if the C portion of your testbench is simulation clock aware at all? If not, how hard would it be for you to create a time aware layer in your C code?

    The solution, I had in mind was to run your C application as an SC_THREAD in systemC. You can make the SC_THREAD sensitive to the clock in verilog design. SC_THREAD in systemC can consume time by waiting on event. You can therefore modify your read and write methods to be something like this:

    while (read_not_done_in_verilog)
    {
    wait until next clock edge;
    if (read_done_in_verilog)
    {

    }
    }


    Originally posted in cdnusers.org by nitin_sharma
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