• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. Manipulating Packed Arrays (structures) using DPI

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 64
  • Views 17257
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Manipulating Packed Arrays (structures) using DPI

archive
archive over 18 years ago

I'm sharing this code which is a demo of how to manipulate a SystemVerilog Packed Array (SV data structure) using DPI. Unpacked refers to anything on the left side of an array. logic [7:0] my_array [1023:0] |-- packed |-- unpacked This code will work with IUS5.83. ----file: top.v------------ module top (); // import functions do a call from SV to C import "DPI-C" context addone_c= function int addone_sv(input int x); import "DPI-C" context function void show_vec_inC(input bit [31:0] some_vec); import "DPI-C" context function void show_logic_inC(input logic [31:0] some_vec); typedef struct packed { int a; bit [9:0] b; bit [5:0] c; } mydata_struct_s; import "DPI-C" context function void pass_struct(inout mydata_struct_s t ); bit [31:0] some_vec = 32'h12345678; logic [31:0] some_logic = 32'h8765X32Z; mydata_struct_s mydata_struct_i; initial begin $display("Gimme_Int %d",addone_sv(5)); show_vec_inC(some_vec); // pass reference per SV spec show_logic_inC(some_logic); // pass reference per SV spec // stuff the structure with data mydata_struct_i.a = 9; mydata_struct_i.b = 10'b10_1011_0110; mydata_struct_i.c = 6'b11_0101; pass_struct(mydata_struct_i); // pass reference to packed struct $display("Verilog a %d", mydata_struct_i.a); $display("Verilog b %h", mydata_struct_i.b); $display("Verilog c %h", mydata_struct_i.c); end endmodule --------file: mydpi.c---------------- #include #include // Copyright Cadence Design Systems, Todd Mackett 2007 // This is an example of manipulating packed data structure in SystemVerilog // Use /tools/inca/include/svdpi.h as a reference int addone_c(int x) { return x +1; } void show_vec_inC(svBitVecVal* x) { io_printf("show_vec_inC\n"); io_printf("a= %x\n", *x); } // svLogicVecVal can have 0,1,X,Z void show_logic_inC(svLogicVecVal* x) { io_printf("show_Logic_inC\n"); io_printf("a= %x\n", *x); io_printf("aval %x\n", x->a); // identical to aval bval as in PLI io_printf("bval %x\n", x->b); } // use VPI io_printf() instead of printf() to go to ncsim.log file void pass_struct( svBitVecVal* x) { // NOT const so that this can be modified // can use x[0] to reference raw array // io_printf("Struct = %x, %x\n", x[0], x[1] ); svBitVecVal aa; // define a local svBitVecVal // extract field a of SV "struct packed {...} mydata_struct_s svGetPartselBit(&aa , x, 16, 32); // corresponds to mydata_struct.a io_printf("mydata_struct_s.a: %x \n", aa); svGetPartselBit(&aa , x, 6, 10); // corresponds to mydata_struct.b io_printf("mydata_struct_s.b: %x \n", aa); svGetPartselBit(&aa , x, 0, 6); // corresponds to mydata_struct.c io_printf("mydata_struct_s.c: %x \n", aa); io_printf("AA %x \n", aa); // do some manipulation on the local svBitVecVal aa = ~aa; // invert the bits (some generic bit manipulation routine) // can do something like this too: just set the value of Verilog Structure // aa = 13; io_printf("AA %x \n", aa); svPutPartselBit(x, aa, 0, 6); // this will modify the Verilog structure } -----file: RUN_NC (script)----- rm -r INCA_libs rm *.so rm *.log rm *.h # Create .h file for Exported tasks/functions only # (imported function do NOT need .h file): ncverilog +sv top.v +ncdpiheader+dpi.h +elaborate +ncelabargs+-messages # ncvlog -sv top.v -mess # ncelab top -sv -dpiheader dpi.h -mess gcc -fPIC -shared -o mydpi.so mydpi.c -I/`ncroot`/tools/inca/include ncverilog +sv top.v +sv_lib=mydpi.so +ncsimargs+"-sv_root ./" ------file: ncverilog.log---------- ncsim> run Gimme_Int 6 show_vec_inC a= 12345678 show_Logic_inC a= 8765f320 aval 8765f320 bval f00f mydata_struct_s.a: 9 mydata_struct_s.b: 2b6 mydata_struct_s.c: 35 AA 35 AA ffffffca Verilog a 9 Verilog b 2b6 Verilog c 0a ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit TOOL: ncverilog 05.83-p003:


Originally posted in cdnusers.org by tmackett
  • Cancel
Parents
  • archive
    archive over 17 years ago

    I'm just updating this topic to let people know that you can use irun to far more easily by doing this: irun mydpi.c top.sv #include #include // This is an example of manipulating packed data structure in SystemVerilog // Use /tools/inca/include/svdpi.h as a reference int addone_c(int x) { return x +1; } void show_vec_inC(svBitVecVal* x) { io_printf("show_vec_inC\n"); io_printf("a= %x\n", *x); } // svLogicVecVal can have 0,1,X,Z void show_logic_inC(svLogicVecVal* x) { io_printf("show_Logic_inC\n"); io_printf("a= %x\n", *x); io_printf("aval %x\n", x->a); // identical to aval bval as in PLI io_printf("bval %x\n", x->b); } // use VPI io_printf() instead of printf() to go to ncsim.log file void pass_struct( svBitVecVal* x) { // NOT const so that this can be modified // can use x[0] to reference raw array // io_printf("Struct = %x, %x\n", x[0], x[1] ); svBitVecVal aa; // define a local svBitVecVal // extract field a of SV "struct packed {...} mydata_struct_s svGetPartselBit(&aa , x, 16, 32); // corresponds to mydata_struct.a io_printf("mydata_struct_s.a: %x \n", aa); svGetPartselBit(&aa , x, 6, 10); // corresponds to mydata_struct.b io_printf("mydata_struct_s.b: %x \n", aa); svGetPartselBit(&aa , x, 0, 6); // corresponds to mydata_struct.c io_printf("mydata_struct_s.c: %x \n", aa); io_printf("AA %x \n", aa); // do some manipulation on the local svBitVecVal aa = ~aa; // invert the bits (some generic bit manipulation routine) // can do something like this too: just set the value of Verilog Structure // aa = 13; io_printf("AA %x \n", aa); svPutPartselBit(x, aa, 0, 6); // this will modify the Verilog structure }


    Originally posted in cdnusers.org by tmackett
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • archive
    archive over 17 years ago

    I'm just updating this topic to let people know that you can use irun to far more easily by doing this: irun mydpi.c top.sv #include #include // This is an example of manipulating packed data structure in SystemVerilog // Use /tools/inca/include/svdpi.h as a reference int addone_c(int x) { return x +1; } void show_vec_inC(svBitVecVal* x) { io_printf("show_vec_inC\n"); io_printf("a= %x\n", *x); } // svLogicVecVal can have 0,1,X,Z void show_logic_inC(svLogicVecVal* x) { io_printf("show_Logic_inC\n"); io_printf("a= %x\n", *x); io_printf("aval %x\n", x->a); // identical to aval bval as in PLI io_printf("bval %x\n", x->b); } // use VPI io_printf() instead of printf() to go to ncsim.log file void pass_struct( svBitVecVal* x) { // NOT const so that this can be modified // can use x[0] to reference raw array // io_printf("Struct = %x, %x\n", x[0], x[1] ); svBitVecVal aa; // define a local svBitVecVal // extract field a of SV "struct packed {...} mydata_struct_s svGetPartselBit(&aa , x, 16, 32); // corresponds to mydata_struct.a io_printf("mydata_struct_s.a: %x \n", aa); svGetPartselBit(&aa , x, 6, 10); // corresponds to mydata_struct.b io_printf("mydata_struct_s.b: %x \n", aa); svGetPartselBit(&aa , x, 0, 6); // corresponds to mydata_struct.c io_printf("mydata_struct_s.c: %x \n", aa); io_printf("AA %x \n", aa); // do some manipulation on the local svBitVecVal aa = ~aa; // invert the bits (some generic bit manipulation routine) // can do something like this too: just set the value of Verilog Structure // aa = 13; io_printf("AA %x \n", aa); svPutPartselBit(x, aa, 0, 6); // this will modify the Verilog structure }


    Originally posted in cdnusers.org by tmackett
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information