• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
  3. Verilog/SystemVerilog mixing ncsim Fatal error?

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 64
  • Views 3208
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Verilog/SystemVerilog mixing ncsim Fatal error?

archive
archive over 18 years ago

When I run Verilog/SystemVerilog mixing ncsim, there is Fatal Error.
//-----Linux-----
ncsim: *F,INTERR: INTERNAL ERROR
Observed simulation time : 0 FS + 0
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
  TOOL: ncsim   05.83-p002
  HOSTNAME: shpc035
  OPERATING SYSTEM: Linux 2.4.21-32.ELsmp #1 SMP Fri Apr 15 21:17:59 EDT 2005 i686
  MESSAGE: sv_seghandler - trapno -1
-----------------------------------------------------------------
***Current stack trace:
 -->[Don't Know      ] 0x83f5812 't know>       
 
//-----SunOS-----
ncsim: *F,INTERR: INTERNAL ERROR
Observed simulation time : 0 FS + 0
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
  TOOL: ncsim   05.83-p002
  HOSTNAME: sh11
  OPERATING SYSTEM: SunOS 5.8 Generic_117350-36 sun4u
  MESSAGE: sv_bushandler - SIGBUS fault address not odd (0x1a42)
-----------------------------------------------------------------
***Current stack trace:
 -->[Don't Know      ] 458578    sss_tag_dbstart      + 72e8   
 -->[Don't Know      ] 405b78    sss_tag_pvsstart     + 5d8    
 -->[Don't Know      ] 379f84    Strap_doAllEvents_   + 1c8c8  
 -->[Don't Know      ] 37abfc    Strap_doAllEvents_   + 1d540  
 -->[Don't Know      ] 15956d8   't know>       
 -->[Don't Know      ] 144e878   't know>       
 -->[Don't Know      ] 4099c4    sss_tag_misc1end     + 2394   
 -->[Don't Know      ] 40a74c    sss_tag_misc1end     + 311c   
 -->[CMD RUN/CMD Overhead] 38568     simcmd_run           + 73c    
 -->[CMD Overhead    ] 3a12c     simcmd_tag_runend    + 84     


Originally posted in cdnusers.org by davyzhu
  • Cancel
Parents
  • archive
    archive over 18 years ago

    Hi,

    I have tried the IUS-583-S003, the old problem pass. Thanks!

    Best regards,
    Davy


    Originally posted in cdnusers.org by davyzhu
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • archive
    archive over 18 years ago

    Hi,

    I have tried the IUS-583-S003, the old problem pass. Thanks!

    Best regards,
    Davy


    Originally posted in cdnusers.org by davyzhu
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information